diff options
| author | Peng Fan <[email protected]> | 2020-05-11 16:41:07 +0800 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2020-05-25 11:54:53 -0400 |
| commit | b4b26192112bd2c225b8e424c2e2d360761cd864 (patch) | |
| tree | cc3e143494ace3b5b27a66ed568d5159ca2da079 | |
| parent | 9c5fef577494769e3ff07952a85f9b7125ef765b (diff) | |
armv8: cache_v8: fix mmu_set_region_dcache_behaviour
The enum dcache_optoion contains a shift left 2 bits in the armv8 case
already. The PMD_ATTRINDX(option) macro will perform a left shift of 2
bits. Perform a right shift so that in the end we get the correct
value.
[trini: Reword the commit message]
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 7ebcaa21a16..7c31d98a6f0 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -557,7 +557,7 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level) void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { - u64 attrs = PMD_ATTRINDX(option); + u64 attrs = PMD_ATTRINDX(option >> 2); u64 real_start = start; u64 real_size = size; |