diff options
| author | Michael Bode <[email protected]> | 2025-05-21 11:47:32 +0200 |
|---|---|---|
| committer | Fabio Estevam <[email protected]> | 2025-05-21 07:53:13 -0300 |
| commit | b7b301c9061401eaea34e19e65cb1862269c9001 (patch) | |
| tree | 77dc4029991fd4c5b49c7eaace145c1bef475319 | |
| parent | 6c885d9ac6306bfe52e5a3b4bcc920112efd8d0b (diff) | |
board: bsh: imx6ulz_smm_m2: Add delay between DRAM read access
A small delay between DRAM read access with wrong parameters and
reconfiguration is necessary.
Without a delay between DRAM read access and a following reconfiguration
this reconfiguration fails for certain DRAM chips (Nanya).
Signed-off-by: Michael Bode <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
| -rw-r--r-- | board/bsh/imx6ulz_smm_m2/spl.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index e8255b6d2a6..c330e4d6d39 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -13,6 +13,7 @@ #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> +#include <linux/delay.h> #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> @@ -65,10 +66,12 @@ static void spl_dram_init(void) /* Already configured, nothing to do */ break; case SZ_256M: + udelay(1); ddr_cfg_write(&bsh_dram_timing_256mb); break; case SZ_128M: default: + udelay(1); ddr_cfg_write(&bsh_dram_timing_128mb); break; } |