diff options
| author | Marek Vasut <[email protected]> | 2022-02-26 04:37:42 +0100 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2022-04-12 15:36:17 +0200 |
| commit | b8a24e07b2bc8648277cb0ca8f6fb814e1e5fdb4 (patch) | |
| tree | 32299442a7e36a745484be921dc0f06856f73acc | |
| parent | 4ca42af8f5b6be986aa9c6b6b87b96a169eb9e77 (diff) | |
imx8m: ddrphy_utils: Add 3732 MT/s mode
Add entry for 3732 MT/s mode of operation of the LPDDR4, in
which case the DDR PLL has to be configured in 933 MHz mode.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
| -rw-r--r-- | drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 0f8baefb1f8..a54449e5f14 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -117,6 +117,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(1000)); dram_disable_bypass(); break; + case 3732: + dram_pll_init(MHZ(933)); + dram_disable_bypass(); + break; case 3200: dram_pll_init(MHZ(800)); dram_disable_bypass(); |