diff options
| author | Tom Rini <[email protected]> | 2025-07-09 08:45:33 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-07-09 08:45:33 -0600 |
| commit | bbca681cde3f0859847bd542e491294fd9d67656 (patch) | |
| tree | d034233a9e8ec209ee5193c7cdef27ef986f9807 | |
| parent | 971bd7614c5df1b77063fab9b0a5cae6afc77d3b (diff) | |
| parent | 48b1f8a396bfe1b29d2033f3d23861a3f470de58 (diff) | |
Merge patch series "board: ti: am33xx: Add Ethernet support for Beaglebone Green Eco"
Romain Gantois <[email protected]> says:
This is version one of my series which enables Ethernet support on the BBGE
board. This requires three main changes:
- Describing the MAC<->PHY link and DP83867 PHY accurately in the device
tree
- Enabling the RGMII1 pinmux configuration
- Enabling the DP83867 driver
These changes are all applied in patch 2.
Patch 1 enables excluding the DP83867 driver from SPL. This is done to
avoid size issues when adding the DP83867 driver to the am335x-evm
defconfig.
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm/dts/am335x-bonegreen-eco.dts | 19 | ||||
| -rw-r--r-- | board/ti/am335x/mux.c | 3 | ||||
| -rw-r--r-- | configs/am335x_evm_defconfig | 1 | ||||
| -rw-r--r-- | drivers/net/phy/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/net/phy/Makefile | 2 |
5 files changed, 28 insertions, 1 deletions
diff --git a/arch/arm/dts/am335x-bonegreen-eco.dts b/arch/arm/dts/am335x-bonegreen-eco.dts index f3363d1ebcc..1e9d7fed3fd 100644 --- a/arch/arm/dts/am335x-bonegreen-eco.dts +++ b/arch/arm/dts/am335x-bonegreen-eco.dts @@ -7,6 +7,7 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" #include "am335x-bonegreen-common.dtsi" +#include <dt-bindings/net/ti-dp83867.h> / { model = "TI AM335x BeagleBone Green Eco"; @@ -25,6 +26,24 @@ interrupt-names = "mc"; }; +&cpsw_emac0 { + phy-mode = "rgmii-id"; + phy-handle = <&dp83867_0>; +}; + +&davinci_mdio { + /delete-node/ ethernet-phy@0; + + dp83867_0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + &baseboard_eeprom { /delete-property/ vcc-supply; }; diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index d416d88c1a1..d2d87c304f6 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -456,6 +456,9 @@ void enable_board_pin_mux(void) if (subtype_id == 'L') configure_module_pin_mux(spi0_pin_mux); + } else if (board_is_bbge()) { + /* Beaglebone Green Eco pinmux */ + configure_module_pin_mux(rgmii1_pin_mux); } else { /* Beaglebone LT pinmux */ configure_module_pin_mux(mii1_pin_mux); diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 208bbb163f4..e1dac88a46f 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -91,6 +91,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_SMSC=y +CONFIG_PHY_TI_DP83867=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 3132718e4f8..8d88c142900 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -314,6 +314,10 @@ config PHY_TI_DP83867 ---help--- Adds support for the TI DP83867 1Gbit PHY. +config SPL_PHY_TI_DP83867 + select PHY_TI + bool "Texas Instruments Ethernet DP83867 PHY support (SPL)" + config PHY_TI_DP83869 select PHY_TI bool "Texas Instruments Ethernet DP83869 PHY support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 2487f366e1c..a119eb5e177 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -32,7 +32,7 @@ obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI_GENERIC) += ti_phy_init.o -obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o +obj-$(CONFIG_$(PHASE_)PHY_TI_DP83867) += dp83867.o obj-$(CONFIG_PHY_TI_DP83869) += dp83869.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o |
