diff options
| author | Andre Przywara <[email protected]> | 2025-05-11 00:33:02 +0100 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2025-06-24 13:44:48 +0100 |
| commit | be5038f168effb23175ecc824b23335cdbcd000e (patch) | |
| tree | 39a0553b4dffa16e6987187659612656e623c087 | |
| parent | 1cc93d42b241d0d077c5a6acda7dc83a9295bb86 (diff) | |
sunxi: add support for Liontron H-A133L board
The Liontron H-A133L is an industrial development board based on the
Allwinner A133 SoC. It uses LPDDR4 DRAM, eMMC, and an AXP707 PMIC.
Add a defconfig with the required DRAM settings.
Signed-off-by: Andre Przywara <[email protected]>
| -rw-r--r-- | board/sunxi/MAINTAINERS | 5 | ||||
| -rw-r--r-- | configs/liontron-h-a133l_defconfig | 37 |
2 files changed, 42 insertions, 0 deletions
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 84799879e85..46094edb3d3 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -296,6 +296,11 @@ M: Adam Sampson <[email protected]> S: Maintained F: configs/Linksprite_pcDuino3_Nano_defconfig +LIONTRON H-A133L BOARD +M: Andre Przywara <[email protected]> +S: Maintained +F: configs/liontron-h-a133l_defconfig + MARSBOARD-A10 BOARD M: Aleksei Mamlin <[email protected]> S: Maintained diff --git a/configs/liontron-h-a133l_defconfig b/configs/liontron-h-a133l_defconfig new file mode 100644 index 00000000000..4b769768e5f --- /dev/null +++ b/configs/liontron-h-a133l_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-a133-liontron-h-a133l" +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x7070707 +CONFIG_DRAM_SUNXI_DX_DRI=0xd0d0d0d +CONFIG_DRAM_SUNXI_CA_DRI=0xe0e +CONFIG_DRAM_SUNXI_PARA0=0xd0a050c +CONFIG_DRAM_SUNXI_MR11=0x4 +CONFIG_DRAM_SUNXI_MR12=0x72 +CONFIG_DRAM_SUNXI_MR13=0x0 +CONFIG_DRAM_SUNXI_MR14=0x7 +CONFIG_DRAM_SUNXI_TPR1=0x26 +CONFIG_DRAM_SUNXI_TPR2=0x6060606 +CONFIG_DRAM_SUNXI_TPR3=0x84040404 +CONFIG_DRAM_SUNXI_TPR6=0x48000000 +CONFIG_DRAM_SUNXI_TPR10=0x273333 +CONFIG_DRAM_SUNXI_TPR11=0x231d151c +CONFIG_DRAM_SUNXI_TPR12=0x1212110e +CONFIG_DRAM_SUNXI_TPR13=0x7521 +CONFIG_DRAM_SUNXI_TPR14=0x2023211f +CONFIG_MACH_SUN50I_A133=y +CONFIG_DRAM_CLK=792 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_SUNXI_DRAM_A133_LPDDR4=y +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_AXP803_POWER=y +CONFIG_AXP_DCDC5_VOLT=1100 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y |