diff options
| author | Tom Rini <[email protected]> | 2025-11-02 11:00:03 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-11-02 12:15:23 -0600 |
| commit | c2637036b8f0c90a2cfc59900f7da31eae646b03 (patch) | |
| tree | dd4f9326cc3bf9f12329a83f77c3b115420842ab | |
| parent | 62b45e82bdbf703571450e97f605893fe0d50530 (diff) | |
| parent | 52ac12235632e8d902f21b572b555b1a415c6c26 (diff) | |
Merge tag 'u-boot-rockchip-20251101' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/28119
- New Boards support:
rk3588: MNT Reform2
rk3528: Radxa ROCK 2A/2F
rk3576: ArmSoM Sige1, Luckfox Omni3576, FriendlyElec NanoPi M5,
Radxa ROCK 4D
rk3568: Lunzn FastRhino R66S
- Other board level updates.
59 files changed, 2031 insertions, 199 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1028764b742..3db5474a05b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2073,30 +2073,30 @@ config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BINMAN if SPL_OPTEE || SPL select DM - select DM_GPIO - select DM_I2C - select DM_PWM - select DM_REGULATOR - select DM_SERIAL - select DM_SPI - select DM_SPI_FLASH select DM_USB_GADGET if USB_DWC3_GADGET select ENABLE_ARM_SOC_BOOT0_HOOK select OF_CONTROL - select MMC - select MTD - select SPI select SPL_DM if SPL - select SPL_DM_SPI if SPL - select SPL_DM_SPI_FLASH if SPL select SYS_MALLOC_F select SYS_THUMB_BUILD if !ARM64 imply ADC + imply BOOTSTD_DEFAULTS imply CMD_DM imply DEBUG_UART_BOARD_INIT - imply BOOTSTD_DEFAULTS + imply DM_GPIO + imply DM_I2C + imply DM_PWM + imply DM_REGULATOR + imply DM_SERIAL + imply DM_SPI + imply DM_SPI_FLASH imply FAT_WRITE + imply MMC + imply MTD imply SARADC_ROCKCHIP + imply SPI + imply SPL_DM_SPI if SPL + imply SPL_DM_SPI_FLASH if SPL imply SPL_SYSRESET imply SPL_SYS_MALLOC_SIMPLE imply SYS_NS16550 diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index a0ab8b69f2e..170e0f7d847 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -3,83 +3,33 @@ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH */ -#include "rockchip-u-boot.dtsi" +#include "rk3326-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = &sdmmc; - }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdmmc; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &sfc; - }; - - dmc { - bootph-all; - compatible = "rockchip,px30-dmc", "syscon"; - reg = <0x0 0xff2a0000 0x0 0x1000>; - }; - - rng: rng@ff0b0000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xff0b0000 0x0 0x4000>; - status = "okay"; - }; -}; - -/* U-Boot clk driver for px30 cannot set GPU_CLK */ -&cru { - bootph-all; - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <17000000>; -}; - -&gpio0 { - bootph-all; - gpio-ranges = <&pinctrl 0 0 32>; -}; - -&gpio1 { - bootph-all; - gpio-ranges = <&pinctrl 0 32 32>; -}; - -&gpio2 { - bootph-all; - gpio-ranges = <&pinctrl 0 64 32>; +&blue_led { + default-state = "on"; + u-boot,default-brightness = <127>; }; -&gpio3 { - bootph-all; - gpio-ranges = <&pinctrl 0 96 32>; +&i2c0_xfer { + bootph-pre-ram; }; -&grf { - bootph-all; +&i2s1_2ch_mclk { + bootph-pre-ram; }; -&pmucru { - bootph-all; +&pcfg_pull_none_smt { + bootph-pre-ram; }; -&pmugrf { - bootph-all; +&pmic_int { + bootph-pre-ram; }; &rk817 { regulators { + bootph-pre-ram; + vcc_cam: LDO_REG9 { regulator-name = "vcc_cam"; regulator-min-microvolt = <3000000>; @@ -94,35 +44,28 @@ }; &saradc { - bootph-all; - status = "okay"; -}; - -&sdmmc { - bootph-all; - - /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ - u-boot,spl-fifo-mode; + bootph-pre-ram; + vdd-microvolts = <1800000>; }; &sfc { - bootph-all; -}; - -&{/spi@ff3a0000/flash@0} { - bootph-all; + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; &uart1 { - clock-frequency = <24000000>; bootph-all; + clock-frequency = <24000000>; }; -&uart2 { - clock-frequency = <24000000>; - bootph-all; +&uart1_cts { + bootph-pre-sram; + bootph-pre-ram; }; -&xin24m { - bootph-all; +&uart1_xfer { + bootph-pre-sram; + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi new file mode 100644 index 00000000000..89b2d9573ad --- /dev/null +++ b/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3326-odroid-go2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi new file mode 100644 index 00000000000..89b2d9573ad --- /dev/null +++ b/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3326-odroid-go2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3326-u-boot.dtsi b/arch/arm/dts/rk3326-u-boot.dtsi new file mode 100644 index 00000000000..6503a9382b9 --- /dev/null +++ b/arch/arm/dts/rk3326-u-boot.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + */ + +#include "rockchip-u-boot.dtsi" + +/ { + aliases { + spi2 = &sfc; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc; + }; + + dmc { + compatible = "rockchip,px30-dmc", "syscon"; + reg = <0x0 0xff2a0000 0x0 0x1000>; + bootph-all; + }; + + rng: rng@ff0b0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff0b0000 0x0 0x4000>; + }; +}; + +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x10000>; + }; + }; +}; +#endif + +&cru { + bootph-all; +}; + +&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + +&grf { + bootph-all; +}; + +&otp { + bootph-some-ram; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_none_8ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pmucru { + bootph-all; +}; + +&pmugrf { + bootph-all; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&sdmmc_bus4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc { + bootph-some-ram; + u-boot,spl-sfc-no-dma; +}; + +&sfc_bus2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc_cs0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart2m1_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index b0e50a973a8..8ffc9ed3d57 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -132,6 +132,10 @@ bootph-pre-ram; }; +&spi0 { + bootph-some-ram; +}; + &uart2 { bootph-all; clock-frequency = <24000000>; diff --git a/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi b/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi new file mode 100644 index 00000000000..3e2fbd81da1 --- /dev/null +++ b/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 16c47e6b9a9..e8c8dc2f032 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -2,8 +2,9 @@ #include "rk3528-u-boot.dtsi" -&sdhci { - mmc-hs200-1_8v; +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; }; &vdd_arm { diff --git a/arch/arm/dts/rk3528-rock-2-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2-u-boot.dtsi new file mode 100644 index 00000000000..e8c8dc2f032 --- /dev/null +++ b/arch/arm/dts/rk3528-rock-2-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; +}; + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; diff --git a/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi new file mode 100644 index 00000000000..bd35ef88298 --- /dev/null +++ b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-rock-2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi new file mode 100644 index 00000000000..bd35ef88298 --- /dev/null +++ b/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-rock-2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi new file mode 100644 index 00000000000..a2b60da6586 --- /dev/null +++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk356x-u-boot.dtsi" diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 87186973953..738b9673d35 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -157,6 +157,7 @@ }; &sfc { + bootph-some-ram; u-boot,spl-sfc-no-dma; }; diff --git a/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi b/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi new file mode 100644 index 00000000000..28773696b97 --- /dev/null +++ b/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +&green_led { + default-state = "on"; +}; + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi b/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi new file mode 100644 index 00000000000..0767fbb8168 --- /dev/null +++ b/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +&led1 { + default-state = "off"; +}; + +&led2 { + default-state = "off"; +}; + +&led_sys { + default-state = "on"; +}; + +&sfc1 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi new file mode 100644 index 00000000000..db46553b66a --- /dev/null +++ b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +&sfc0 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index fb5a107f47d..dc3771b556a 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -6,6 +6,11 @@ #include "rockchip-u-boot.dtsi" / { + aliases { + spi5 = &sfc0; + spi6 = &sfc1; + }; + chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; @@ -16,6 +21,17 @@ }; }; +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x8000>; + }; + }; +}; +#endif + &cru { bootph-all; }; @@ -45,6 +61,26 @@ bootph-some-ram; }; +&fspi0_csn0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&fspi0_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&fspi1m1_csn0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&fspi1m1_pins { + bootph-pre-ram; + bootph-some-ram; +}; + &ioc_grf { bootph-all; }; @@ -116,6 +152,16 @@ bootph-some-ram; }; +&sfc0 { + bootph-some-ram; + u-boot,spl-sfc-no-dma; +}; + +&sfc1 { + bootph-some-ram; + u-boot,spl-sfc-no-dma; +}; + &sys_grf { bootph-all; }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 5eeb138f351..71fd352f640 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -140,6 +140,7 @@ }; &sfc { + bootph-some-ram; u-boot,spl-sfc-no-dma; }; diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index e736772fda7..b15938c021d 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -64,4 +64,6 @@ extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; */ #define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10) +u32 read_brom_bootsource_id(void); + #endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index ae15a9f8a2d..06fb527b21a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,9 +11,9 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o spl_common.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o -obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o spl_common.o -obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o spl_common.o ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c index f0b3c5f83f4..2a3dcdac845 100644 --- a/arch/arm/mach-rockchip/px30-board-tpl.c +++ b/arch/arm/mach-rockchip/px30-board-tpl.c @@ -4,32 +4,9 @@ */ #include <debug_uart.h> -#include <dm.h> -#include <init.h> -#include <ram.h> -#include <spl.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/sdram_px30.h> - -#define TIMER_LOAD_COUNT0 0x00 -#define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CUR_VALUE0 0x08 -#define TIMER_CUR_VALUE1 0x0c -#define TIMER_CONTROL_REG 0x10 - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) -{ - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1); - writel(TIMER_EN | TIMER_FMODE, - CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); -} +#include <asm/arch-rockchip/timer.h> void board_init_f(ulong dummy) { @@ -50,7 +27,8 @@ void board_init_f(ulong dummy) #endif #endif - secure_timer_init(); + rockchip_stimer_init(); + ret = sdram_init(); if (ret) printascii("sdram_init failed\n"); diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 64e100172fa..d69139278a8 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -5,28 +5,9 @@ #include <debug_uart.h> #include <init.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/sdram_rk3036.h> - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void rockchip_stimer_init(void) -{ - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(CONFIG_COUNTER_FREQUENCY)); - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} +#include <asm/arch-rockchip/timer.h> void board_init_f(ulong dummy) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 43d151708e4..8687a9347ec 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -61,8 +61,8 @@ struct mm_region *mem_map = rk3399_mem_map; #define TIMER_CONTROL_REG 0x1c #define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) void rockchip_stimer_init(void) { diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig index 993b2dd274e..480ac2942ff 100644 --- a/arch/arm/mach-rockchip/rk3528/Kconfig +++ b/arch/arm/mach-rockchip/rk3528/Kconfig @@ -1,5 +1,10 @@ if ROCKCHIP_RK3528 +config TARGET_RADXA_ROCK_2_RK3528 + bool "Radxa ROCK 2A/2F" + help + Radxa ROCK 2A/2F single board computers with a RK3528A SoC. + config ROCKCHIP_BOOT_MODE_REG default 0xff370200 @@ -9,6 +14,8 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3528" +source "board/radxa/rock-2-rk3528/Kconfig" + config SYS_CONFIG_NAME default "rk3528_common" diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS index f343f71cf7f..ee840396e8b 100644 --- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS @@ -9,3 +9,9 @@ M: Jonas Karlman <[email protected]> S: Maintained F: arch/arm/dts/rk3528-radxa-e20c* F: configs/radxa-e20c-rk3528_defconfig + +SIGE1-RK3528 +M: Jonas Karlman <[email protected]> +S: Maintained +F: arch/arm/dts/rk3528-armsom-sige1* +F: configs/sige1-rk3528_defconfig diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index f9bfc445b85..57ead0006f1 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -49,6 +49,21 @@ void board_debug_uart_init(void) { } +u32 read_brom_bootsource_id(void) +{ + u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); + + /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE + * enum value to avoid having to create a larger boot_devices table. + */ + if (bootsource_id == 0x81) + return BROM_BOOTSOURCE_USB; + else if (bootsource_id > BROM_LAST_BOOTSOURCE) + log_debug("Unknown bootsource %x\n", bootsource_id); + + return bootsource_id; +} + int arch_cpu_init(void) { u32 val; diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS index 94ef74d429f..393edd3984c 100644 --- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -4,6 +4,24 @@ S: Maintained F: arch/arm/dts/rk3576-generic* F: configs/generic-rk3576_defconfig +NANOPI-M5-RK3576 +M: Jonas Karlman <[email protected]> +S: Maintained +F: arch/arm/dts/rk3576-nanopi-m5* +F: configs/nanopi-m5-rk3576_defconfig + +OMNI3576-RK3576 +M: Jonas Karlman <[email protected]> +S: Maintained +F: arch/arm/dts/rk3576-luckfox-omni3576* +F: configs/omni3576-rk3576_defconfig + +ROCK-4D-RK3576 +M: Jonas Karlman <[email protected]> +S: Maintained +F: arch/arm/dts/rk3576-rock-4d* +F: configs/rock-4d-rk3576_defconfig + SIGE5-RK3576 M: Jonas Karlman <[email protected]> S: Maintained diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index a6c2fbdc484..a1e8a7572fa 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -36,8 +36,15 @@ #define USB_GRF_BASE 0x2601E000 #define USB3OTG0_CON1 0x0030 +enum { + BROM_BOOTSOURCE_FSPI0 = 3, + BROM_BOOTSOURCE_FSPI1_M1 = 6, +}; + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", + [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0", + [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", }; @@ -85,6 +92,24 @@ void board_debug_uart_init(void) { } +u32 read_brom_bootsource_id(void) +{ + u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); + + /* Re-map the raw value read from reg to a redefined or existing + * BROM_BOOTSOURCE enum value to avoid having to create a larger + * boot_devices table. + */ + if (bootsource_id == 0x23) + return BROM_BOOTSOURCE_FSPI1_M1; + else if (bootsource_id == 0x81) + return BROM_BOOTSOURCE_USB; + else if (bootsource_id > BROM_LAST_BOOTSOURCE) + log_debug("Unknown bootsource %x\n", bootsource_id); + + return bootsource_id; +} + #define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE #define HP_CTRL_REG 0x04 #define TIMER_EN BIT(0) diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 561bddd12a6..1ea1033b5ea 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -40,7 +40,7 @@ static int spl_node_to_boot_device(int node) * aware of the block-device layer. Until then (and to avoid unneeded * delays in getting this feature out), it lives at the board-level. */ - if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { + if (!uclass_find_device_by_of_offset(UCLASS_MMC, node, &parent)) { struct udevice *dev; struct blk_desc *desc = NULL; @@ -72,7 +72,7 @@ static int spl_node_to_boot_device(int node) * extended with awareness of the BLK layer (and matching OF_CONTROL) * soon. */ - if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) return BOOT_DEVICE_SPI; return -1; diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index f4d29bbdd17..1ce3a3b0554 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -31,6 +31,11 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { }; +__weak u32 read_brom_bootsource_id(void) +{ + return readl(BROM_BOOTSOURCE_ID_ADDR); +} + const char *board_spl_was_booted_from(void) { static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN; @@ -40,7 +45,7 @@ const char *board_spl_was_booted_from(void) if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN) bootdevice_brom_id = brom_bootsource_id_cache; else - bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); + bootdevice_brom_id = read_brom_bootsource_id(); if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) bootdevice_ofpath = boot_devices[bootdevice_brom_id]; diff --git a/arch/arm/mach-rockchip/spl_common.c b/arch/arm/mach-rockchip/spl_common.c index b29f33448ab..208cd22fcad 100644 --- a/arch/arm/mach-rockchip/spl_common.c +++ b/arch/arm/mach-rockchip/spl_common.c @@ -10,8 +10,8 @@ #define TIMER_LOAD_COUNT_H 0x04 #define TIMER_CONTROL_REG 0x10 #define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) __weak void rockchip_stimer_init(void) { diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index c1d1826fd14..d402374e90e 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -695,7 +695,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (gd->board_type == RG353M) fdt_setprop(blob, 0, "model", rg3xx_model_details[RG353M].board_name, - sizeof(rg3xx_model_details[RG353M].board_name)); + strlen(rg3xx_model_details[RG353M].board_name)); if (rg3xx_model_details[gd->board_type].detect_panel) { ret = rgxx3_panel_fixup(blob); diff --git a/board/hardkernel/odroid_go2/Kconfig b/board/hardkernel/odroid_go2/Kconfig index 82988dffb3c..6487335972b 100644 --- a/board/hardkernel/odroid_go2/Kconfig +++ b/board/hardkernel/odroid_go2/Kconfig @@ -9,4 +9,11 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "odroid_go2" +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ADC + select BOARD_TYPES + select ENV_IS_NOWHERE + select SPL_ADC + endif diff --git a/board/hardkernel/odroid_go2/MAINTAINERS b/board/hardkernel/odroid_go2/MAINTAINERS index 9e83bc9452c..ee06c2fa651 100644 --- a/board/hardkernel/odroid_go2/MAINTAINERS +++ b/board/hardkernel/odroid_go2/MAINTAINERS @@ -1,6 +1,8 @@ GO2 M: Heiko Stuebner <[email protected]> +R: Jonas Karlman <[email protected]> S: Maintained F: board/hardkernel/odroid_go2/ F: include/configs/odroid_go2.h +F: arch/arm/dts/rk3326-odroid-go* F: configs/odroid-go2_defconfig diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c index a0338ead3b5..ae32ea87af8 100644 --- a/board/hardkernel/odroid_go2/go2.c +++ b/board/hardkernel/odroid_go2/go2.c @@ -7,9 +7,13 @@ #include <adc.h> #include <asm/io.h> #include <dm.h> +#include <dm/uclass-internal.h> #include <env.h> +#include <env_internal.h> #include <stdlib.h> +DECLARE_GLOBAL_DATA_PTR; + #define DTB_DIR "rockchip/" struct oga_model { @@ -20,7 +24,7 @@ struct oga_model { }; enum oga_device_id { - OGA, + OGA = 1, OGA_V11, OGS, }; @@ -50,15 +54,10 @@ static const struct oga_model oga_model_details[] = { }, }; -/* Detect which Odroid Go Advance device we are using so as to load the - * correct devicetree for Linux. Set an environment variable once - * found. The detection depends on the value of ADC channel 0. - */ -int oga_detect_device(void) +static int oga_read_board_id(void) { u32 adc_info; - int ret, i; - int board_id = -ENXIO; + int i, ret; ret = adc_channel_single_shot("saradc@ff288000", 0, &adc_info); if (ret) { @@ -72,22 +71,32 @@ int oga_detect_device(void) * accounted for this with a 5% tolerance, so assume a +- value * of 50 should be enough. */ - for (i = 0; i < ARRAY_SIZE(oga_model_details); i++) { + for (i = 1; i < ARRAY_SIZE(oga_model_details); i++) { u32 adc_min = oga_model_details[i].adc_value - 50; u32 adc_max = oga_model_details[i].adc_value + 50; - if (adc_min < adc_info && adc_max > adc_info) { - board_id = i; - break; - } + if (adc_min < adc_info && adc_max > adc_info) + return i; } + return -ENODEV; +} + +/* Detect which Odroid Go Advance device we are using so as to load the + * correct devicetree for Linux. Set an environment variable once + * found. The detection depends on the value of ADC channel 0. + */ +static int oga_detect_device(void) +{ + int board_id; + + board_id = oga_read_board_id(); if (board_id < 0) return board_id; + gd->board_type = board_id; env_set("board", oga_model_details[board_id].board); - env_set("board_name", - oga_model_details[board_id].board_name); + env_set("board_name", oga_model_details[board_id].board_name); env_set("fdtfile", oga_model_details[board_id].fdtfile); return 0; @@ -105,3 +114,52 @@ int rk_board_late_init(void) return 0; } + +int board_fit_config_name_match(const char *name) +{ + int board_id; + + if (!gd->board_type) { + board_id = oga_read_board_id(); + if (board_id < 0) + return board_id; + gd->board_type = board_id; + } + + if (!strcmp(name, oga_model_details[gd->board_type].fdtfile)) + return 0; + + return -EINVAL; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + const char *boot_device; + struct udevice *dev; + ofnode node; + + if (prio) + return ENVL_UNKNOWN; + + boot_device = ofnode_read_chosen_string("u-boot,spl-boot-device"); + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", __func__); + return ENVL_NOWHERE; + } + + debug("%s: booted from %s\n", __func__, boot_device); + + node = ofnode_path(boot_device); + if (!ofnode_valid(node)) + return ENVL_NOWHERE; + + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && + !uclass_find_device_by_ofnode(UCLASS_SPI_FLASH, node, &dev)) + return ENVL_SPI_FLASH; + + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) && + !uclass_find_device_by_ofnode(UCLASS_MMC, node, &dev)) + return ENVL_MMC; + + return ENVL_NOWHERE; +} diff --git a/board/radxa/rock-2-rk3528/Kconfig b/board/radxa/rock-2-rk3528/Kconfig new file mode 100644 index 00000000000..5f1ad10c0ed --- /dev/null +++ b/board/radxa/rock-2-rk3528/Kconfig @@ -0,0 +1,14 @@ +if TARGET_RADXA_ROCK_2_RK3528 + +config SYS_BOARD + default "rock-2-rk3528" + +config SYS_VENDOR + default "radxa" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ADC + select SPL_ADC + +endif diff --git a/board/radxa/rock-2-rk3528/MAINTAINERS b/board/radxa/rock-2-rk3528/MAINTAINERS new file mode 100644 index 00000000000..841bd28450f --- /dev/null +++ b/board/radxa/rock-2-rk3528/MAINTAINERS @@ -0,0 +1,6 @@ +RADXA-ROCK-2-RK3528 +M: Jonas Karlman <[email protected]> +S: Maintained +F: board/radxa/rock-2-rk3528 +F: configs/rock-2-rk3528_defconfig +F: arch/arm/dts/rk3528-rock-2* diff --git a/board/radxa/rock-2-rk3528/Makefile b/board/radxa/rock-2-rk3528/Makefile new file mode 100644 index 00000000000..b3e0ad0b540 --- /dev/null +++ b/board/radxa/rock-2-rk3528/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += rock-2-rk3528.o diff --git a/board/radxa/rock-2-rk3528/rock-2-rk3528.c b/board/radxa/rock-2-rk3528/rock-2-rk3528.c new file mode 100644 index 00000000000..2d265b67f0d --- /dev/null +++ b/board/radxa/rock-2-rk3528/rock-2-rk3528.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include <adc.h> +#include <env.h> + +#define HW_ID_CHANNEL 2 + +struct board_model { + unsigned int low; + unsigned int high; + const char *fdtfile; +}; + +static const struct board_model board_models[] = { + { 63, 278, "rockchip/rk3528-rock-2a.dtb" }, + { 291, 392, "rockchip/rk3528-radxa-e20c.dtb" }, + { 519, 733, "rockchip/rk3528-rock-2f.dtb" }, +}; + +static const struct board_model *get_board_model(void) +{ + unsigned int val; + int i, ret; + + ret = adc_channel_single_shot("adc@ffae0000", HW_ID_CHANNEL, &val); + if (ret) + return NULL; + + for (i = 0; i < ARRAY_SIZE(board_models); i++) { + unsigned int min = board_models[i].low; + unsigned int max = board_models[i].high; + + if (min <= val && val <= max) + return &board_models[i]; + } + + return NULL; +} + +int rk_board_late_init(void) +{ + const struct board_model *model = get_board_model(); + + if (model) + env_set("fdtfile", model->fdtfile); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + const struct board_model *model = get_board_model(); + + if (model && !strcmp(name, model->fdtfile)) + return 0; + + return -EINVAL; +} diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 6cf568ad150..030cdbe6f3d 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -14,6 +14,13 @@ F: configs/evb-rk3568_defconfig F: arch/arm/dts/rk3568-evb-u-boot.dtsi F: arch/arm/dts/rk3568-evb.dts +FASTRHINO-R66S-RK3568 +M: Tianling Shen <[email protected]> +R: Jonas Karlman <[email protected]> +S: Maintained +F: configs/fastrhino-r66s-rk3568_defconfig +F: arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi + GENERIC-RK3568 M: Jonas Karlman <[email protected]> S: Maintained diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 379c85f48a4..8b11db43f5f 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -29,6 +29,11 @@ F: configs/generic-rk3588_defconfig F: arch/arm/dts/rk3588-generic.dts F: arch/arm/dts/rk3588-generic-u-boot.dtsi +MNT-REFORM2-RK3588 +M: Peter Robinson <[email protected]> +S: Maintained +F: configs/mnt-reform2-rk3588_defconfig + ORANGEPI-5-RK3588 M: Jonas Karlman <[email protected]> S: Maintained diff --git a/configs/fastrhino-r66s-rk3568_defconfig b/configs/fastrhino-r66s-rk3568_defconfig new file mode 100644 index 00000000000..70b20720eca --- /dev/null +++ b/configs/fastrhino-r66s-rk3568_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r66s" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/mnt-reform2-rk3588_defconfig b/configs/mnt-reform2-rk3588_defconfig new file mode 100644 index 00000000000..c9cd4c85321 --- /dev/null +++ b/configs/mnt-reform2-rk3588_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-mnt-reform2" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start; nvme scan;" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-mnt-reform2" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m5-rk3576_defconfig b/configs/nanopi-m5-rk3576_defconfig new file mode 100644 index 00000000000..28427390a62 --- /dev/null +++ b/configs/nanopi-m5-rk3576_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-m5" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_SF_DEFAULT_BUS=6 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-m5.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 698aad59dec..512ffefc70f 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -3,81 +3,98 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=108000000 +CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_SF_DEFAULT_BUS=2 CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb" -# CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_BANNER_PRINT is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_LZMADEC is not set -# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_LIST="rockchip/rk3326-odroid-go2 rockchip/rk3326-odroid-go2-v11 rockchip/rk3326-odroid-go3" +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_BUF_SIZE=0x04000000 CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_PWM=y +CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_ROCKCHIP_OTP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_PHY_REALTEK=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XTX=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y @@ -85,10 +102,13 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y +CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y CONFIG_USB=y @@ -96,10 +116,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_VIDEO=y -CONFIG_DISPLAY=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_TPL_TINY_MEMSET=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -CONFIG_OPTEE_LIB=y diff --git a/configs/omni3576-rk3576_defconfig b/configs/omni3576-rk3576_defconfig new file mode 100644 index 00000000000..13ef3112f1b --- /dev/null +++ b/configs/omni3576-rk3576_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-luckfox-omni3576" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-luckfox-omni3576.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig index 0941d1b9be8..fa20424ee7b 100644 --- a/configs/radxa-e20c-rk3528_defconfig +++ b/configs/radxa-e20c-rk3528_defconfig @@ -4,12 +4,14 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c" CONFIG_ROCKCHIP_RK3528=y +CONFIG_TARGET_RADXA_ROCK_2_RK3528=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART_BASE=0xFF9F0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb" # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_RNG_SEED=y CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_MEMINFO=y @@ -26,6 +28,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_RNG=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_LIST="rockchip/rk3528-radxa-e20c rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y diff --git a/configs/rock-2-rk3528_defconfig b/configs/rock-2-rk3528_defconfig new file mode 100644 index 00000000000..b9261de460b --- /dev/null +++ b/configs/rock-2-rk3528_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-rock-2a" +CONFIG_ROCKCHIP_RK3528=y +CONFIG_TARGET_RADXA_ROCK_2_RK3528=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFF9F0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-rock-2a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_LIST="rockchip/rk3528-rock-2a rockchip/rk3528-rock-2f rockchip/rk3528-radxa-e20c" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_BUTTON_GPIO=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock-4d-rk3576_defconfig b/configs/rock-4d-rk3576_defconfig new file mode 100644 index 00000000000..140a3e0ccd8 --- /dev/null +++ b/configs/rock-4d-rk3576_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/sige1-rk3528_defconfig b/configs/sige1-rk3528_defconfig new file mode 100644 index 00000000000..bfa070a8e00 --- /dev/null +++ b/configs/sige1-rk3528_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-armsom-sige1" +CONFIG_ROCKCHIP_RK3528=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFF9F0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-armsom-sige1.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index de3aa79cb5c..0acccb51ad5 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -100,8 +100,10 @@ List of mainline supported Rockchip boards: - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399) * rk3528 + - ArmSoM Sige1 (sige1-rk3528) - Generic RK3528 (generic-rk3528) - Radxa E20C (radxa-e20c-rk3528) + - Radxa ROCK 2A/2F (rock-2-rk3528) * rk3566 - Anbernic RGxx3 (anbernic-rgxx3-rk3566) @@ -128,6 +130,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568) - Generic RK3566/RK3568 (generic-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - Lunzn FastRhino R66S (fastrhino-r66s-rk3568) - QNAP TS-433 (qnap-ts433-rk3568) - Radxa E25 Carrier Board (radxa-e25-rk3568) - Radxa ROCK 3A (rock-3a-rk3568) @@ -136,7 +139,10 @@ List of mainline supported Rockchip boards: * rk3576 - ArmSoM Sige5 (sige5-rk3576) - Firefly ROC-RK3576-PC (roc-pc-rk3576) + - FriendlyElec NanoPi M5 (nanopi-m5-rk3576) - Generic RK3576 (generic-rk3576) + - Luckfox Omni3576 (omni3576-rk3576) + - Radxa ROCK 4D (rock-4d-rk3576) * rk3588 - ArmSoM Sige7 (sige7-rk3588) @@ -152,6 +158,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M2 (odroid-m2-rk3588s) - Indiedroid Nova (nova-rk3588s) - Khadas Edge2 (khadas-edge2-rk3588s) + - MNT Reform2 (mnt-reform2-rk3588) - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index ad7e1c0f246..b5054e84c32 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1360,6 +1360,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate) case SCLK_GMAC_RMII: ret = px30_mac_set_speed_clk(priv, rate); break; + /* Might occur in cru assigned-clocks, can be ignored here */ + case SCLK_GPU: + break; #endif default: return -ENOENT; @@ -1726,6 +1729,9 @@ static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) case SCLK_UART0_PMU: ret = px30_pmu_uart0_set_clk(priv, rate); break; + /* Might occur in pmucru assigned-clocks, can be ignored here */ + case SCLK_WIFI_PMU: + break; default: return -ENOENT; } diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 5e025d76a82..8116e464278 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -9,6 +9,7 @@ #include <dm.h> #include <dm/ofnode.h> #include <dt-structs.h> +#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/libfdt.h> @@ -86,6 +87,9 @@ #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) #define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30) +#define DLL_TAPVALUE_FROM_SW BIT(25) +#define DLL_TAP_VALUE_PREP(x) FIELD_PREP(GENMASK(15, 8), (x)) +#define DLL_LOCK_VALUE_GET(x) FIELD_GET(GENMASK(7, 0), (x)) #define DLL_LOCK_WO_TMOUT(x) \ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ @@ -93,6 +97,7 @@ #define ROCKCHIP_MAX_CLKS 3 #define FLAG_INVERTER_FLAG_IN_RXCLK BIT(0) +#define FLAG_TAPVALUE_FROM_SW BIT(1) struct rockchip_sdhc_plat { struct mmc_config cfg; @@ -317,7 +322,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); struct mmc *mmc = host->mmc; int val, ret; - u32 extra, txclk_tapnum; + u32 extra, txclk_tapnum, dll_tap_value; if (!enable) { sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); @@ -347,7 +352,15 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab if (ret) return ret; - extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE; + if (data->flags & FLAG_TAPVALUE_FROM_SW) + dll_tap_value = DLL_TAPVALUE_FROM_SW | + DLL_TAP_VALUE_PREP(DLL_LOCK_VALUE_GET(val) * 2); + else + dll_tap_value = 0; + + extra = DWCMSHC_EMMC_DLL_DLYENA | + DLL_RXCLK_ORI_GATE | + dll_tap_value; if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK) extra |= DLL_RXCLK_NO_INVERTER; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); @@ -361,19 +374,22 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab DLL_CMDOUT_BOTH_CLK_EDGE | DWCMSHC_EMMC_DLL_DLYENA | data->hs400_cmdout_tapnum | - DLL_CMDOUT_TAPNUM_FROM_SW; + DLL_CMDOUT_TAPNUM_FROM_SW | + dll_tap_value; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT); } extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_TXCLK_TAPNUM_FROM_SW | DLL_TXCLK_NO_INVERTER | - txclk_tapnum; + txclk_tapnum | + dll_tap_value; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); extra = DWCMSHC_EMMC_DLL_DLYENA | data->hs400_strbin_tapnum | - DLL_STRBIN_TAPNUM_FROM_SW; + DLL_STRBIN_TAPNUM_FROM_SW | + dll_tap_value; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } else { /* @@ -663,6 +679,7 @@ static const struct sdhci_data rk3528_data = { .set_ios_post = rk3568_sdhci_set_ios_post, .set_clock = rk3568_sdhci_set_clock, .config_dll = rk3568_sdhci_config_dll, + .flags = FLAG_TAPVALUE_FROM_SW, .hs200_txclk_tapnum = 0xc, .hs400_txclk_tapnum = 0x6, .hs400_cmdout_tapnum = 0x6, diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index 73738ab26d3..60e74117057 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -108,6 +108,7 @@ #define SFC_VER_3 0x3 #define SFC_VER_4 0x4 #define SFC_VER_5 0x5 +#define SFC_VER_8 0x8 /* Delay line controller resiter */ #define SFC_DLL_CTRL0 0x3C @@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op return 0; } +#if CONFIG_IS_ENABLED(CLK) +static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed) +{ + if (sfc->version >= SFC_VER_8) + return clk_set_rate(&sfc->clk, speed * 2); + else + return clk_set_rate(&sfc->clk, speed); +} +#endif + static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) { struct rockchip_sfc *sfc = dev_get_plat(bus); @@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) return 0; #if CONFIG_IS_ENABLED(CLK) - int ret = clk_set_rate(&sfc->clk, speed); + int ret = rockchip_sfc_clk_set_rate(sfc, speed); if (ret < 0) { dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", diff --git a/dts/upstream/src/arm64/rockchip/rk3528-armsom-sige1.dts b/dts/upstream/src/arm64/rockchip/rk3528-armsom-sige1.dts new file mode 100644 index 00000000000..6e21579365a --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3528-armsom-sige1.dts @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3528.dtsi" + +/ { + model = "ArmSoM Sige1"; + compatible = "armsom,sige1", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + i2c0 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio0; + serial0 = &uart0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&g_led>, <&r_led>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = <LED_COLOR_ID_RED>; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + vcc0v6_ddr: regulator-0v6-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc0v6_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc1v8_ddr: regulator-1v8-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_dcin>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_dcin>; + }; + + vcc5v0_usb1_host: regulator-5v0-vcc-usb1-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host1_drv_h>; + regulator-name = "vcc5v0_usb1_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2_host: regulator-5v0-vcc-usb2-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host2_drv_h>; + regulator-name = "vcc5v0_usb2_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_otg0_drv_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_dcin: regulator-vcc-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_dcin"; + regulator-always-on; + regulator-boot-on; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>, <&clkm1_32k_out>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + g_led: g-led { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + r_led: r-led { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb20_host1_drv_h: usb20-host1-drv-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb20_host2_drv_h: usb20-host2-drv-h { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb20_otg0_drv_h: usb20-otg0-drv-h { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + clocks = <&cru CLK_DEEPSLOW>; + clock-names = "lpo"; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&uart2 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>, <&uart2m1_ctsn>, <&uart2m1_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&cru CLK_DEEPSLOW>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h>, <&bt_wake_host_h>, <&host_wake_bt_h>; + shutdown-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3528-rock-2.dtsi b/dts/upstream/src/arm64/rockchip/rk3528-rock-2.dtsi new file mode 100644 index 00000000000..aedc7ee9ee4 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3528-rock-2.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3528.dtsi" + +/ { + aliases { + i2c1 = &i2c1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&state_led_b>; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_wifi: regulator-3v3-vcc-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_wifi_pwr>; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb20: regulator-5v0-vcc-usb20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_en>; + regulator-name = "vcc5v0_usb20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; + + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-wlan"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + radio-type = "wlan"; + shutdown-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3>; + }; +}; + +&pinctrl { + bluetooth { + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + state_led_b: state-led-b { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_en: usb-host-en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + usb_wifi_pwr: usb-wifi-pwr { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <100000000>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts b/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts new file mode 100644 index 00000000000..c03ae1dd345 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3528-rock-2.dtsi" + +/ { + model = "Radxa ROCK 2A"; + compatible = "radxa,rock-2a", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + }; + + vcc5v0_usb30_otg: regulator-5v0-vcc-usb30-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_en>; + regulator-name = "vcc5v0_usb30_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&state_led_b>, <&sys_led_g>; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + sys_led_g: sys-led-g { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_otg_en: usb-otg-en { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3528-rock-2f.dts b/dts/upstream/src/arm64/rockchip/rk3528-rock-2f.dts new file mode 100644 index 00000000000..3e2b9b685cb --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3528-rock-2f.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3528-rock-2.dtsi" + +/ { + model = "Radxa ROCK 2F"; + compatible = "radxa,rock-2f", "rockchip,rk3528"; +}; diff --git a/tools/binman/btool/mkimage.py b/tools/binman/btool/mkimage.py index 3f84220fb1a..23c0a8e490d 100644 --- a/tools/binman/btool/mkimage.py +++ b/tools/binman/btool/mkimage.py @@ -35,7 +35,6 @@ class Bintoolmkimage(bintool.Bintool): signatures align: Bytes to use for alignment of the FIT and its external data keys_dir: Path to directory containing private and encryption keys - version: True to get the mkimage version """ args = [] if external: |