diff options
| author | Max Merchel <[email protected]> | 2026-07-13 15:01:04 +0200 |
|---|---|---|
| committer | Fabio Estevam <[email protected]> | 2026-07-27 13:05:07 -0300 |
| commit | c6bf5b6a14e32196b889ff4b27611f883ae3f448 (patch) | |
| tree | 956f1b20251378540660cd5e6877bcb3ddea0bd8 | |
| parent | 2416b2a21cf1289b2c5232d49146964322412bc9 (diff) | |
board: tqma6: use runtime SoC detection in enet setup
Select the appropriate iomux settings based on the CPU type
during ethernet configuration.
Signed-off-by: Paul Gerber <[email protected]>
Signed-off-by: Max Merchel <[email protected]>
| -rw-r--r-- | board/tq/tqma6/tqma6_mba6.c | 33 |
1 files changed, 15 insertions, 18 deletions
diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 32aeb1b07c8..8cc5857b06f 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -33,21 +33,11 @@ #include "../common/tq_bb.h" -#if defined(CONFIG_TQMA6Q) - -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 -#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac - -#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) - -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 -#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 +#define TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 +#define TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac -#else - -#error "need to select module" - -#endif +#define TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 +#define TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 /* disable on die termination for RGMII */ #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 @@ -63,10 +53,17 @@ static void mba6_setup_iomuxc_enet(void) /* clear gpr1[ENET_CLK_SEL] for externel clock */ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, - (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); - __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, - (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + if (is_mx6sdl()) { + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + } else if (is_mx6dq()) { + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + } } int board_mmc_get_env_dev(int devno) |