diff options
| author | Yao Zi <[email protected]> | 2025-06-18 09:54:57 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2025-07-03 18:10:58 +0800 |
| commit | c7e27f9a4a21ac7fd51e2175cf7ab36b5d9812c4 (patch) | |
| tree | e61197bdac822a650c63dfb68ea9e365ab667571 | |
| parent | a4f9013e311de2095148ce3dbe9dadaae812e51b (diff) | |
riscv: cpu: th1520: Enable pinctrl by default
Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.
Signed-off-by: Yao Zi <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
| -rw-r--r-- | arch/riscv/cpu/th1520/Kconfig | 1 | ||||
| -rw-r--r-- | configs/th1520_lpi4a_defconfig | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index 4d44191bd22..c73462c04b8 100644 --- a/arch/riscv/cpu/th1520/Kconfig +++ b/arch/riscv/cpu/th1520/Kconfig @@ -11,6 +11,7 @@ config THEAD_TH1520 select BINMAN if SPL select SYS_CACHE_THEAD_CMO select CLK_THEAD + select PINCTRL_TH1520 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 243b89f753d..39d8c948af1 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -105,3 +105,4 @@ CONFIG_ZLIB_UNCOMPRESS=y CONFIG_BZIP2=y CONFIG_ZSTD=y CONFIG_LIB_RATIONAL=y +CONFIG_PINCTRL=y |