diff options
| author | Balaji Selvanathan <[email protected]> | 2025-12-03 16:37:30 +0530 |
|---|---|---|
| committer | Casey Connolly <[email protected]> | 2026-04-27 12:33:30 +0200 |
| commit | c808ab5fed990e2aa8e4ca6a855db49a225edd64 (patch) | |
| tree | 3a9c83d8261c3046981971f81efdd605d4a5cce8 | |
| parent | 0bbde64361d96000ff4f4ff20d060745064f2b98 (diff) | |
drivers: clk: qcom: sc7280: Add USB3 PHY pipe clock
Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by
the USB3 PHY on SC7280/QCM6490 platforms.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
| -rw-r--r-- | drivers/clk/qcom/clock-sc7280.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 7b6ed826023..403995e5a0a 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -116,6 +116,7 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1), GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf05c, 1), GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1), GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1), GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1), |