diff options
| author | Lokesh Vutla <[email protected]> | 2015-06-04 10:08:50 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2015-06-15 10:57:27 -0400 |
| commit | c997da5c53586e0cb220d94179f922e865cffb62 (patch) | |
| tree | fa43c37a6848a8b6067694d3d62f246ee15a72e1 | |
| parent | 2ce6ecaccaa0b1bea31cdbe05f5f5c54d2468db0 (diff) | |
ARM: DRA7: emif: Fix DDR init sequence during warm reset
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index ca22c006018..f5b22f6a783 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1170,7 +1170,7 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!(in_sdram || warm_reset())) { + if (!in_sdram && (!warm_reset() || is_dra7xx())) { if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); @@ -1178,7 +1178,7 @@ static void do_sdram_init(u32 base) ddr3_init(base, regs); } if (warm_reset() && (emif_sdram_type(regs->sdram_config) == - EMIF_SDRAM_TYPE_DDR3)) { + EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { set_lpmode_selfrefresh(base); emif_reset_phy(base); omap5_ddr3_leveling(base, regs); |