diff options
| author | Sebastien Jan <[email protected]> | 2012-06-13 05:16:40 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <[email protected]> | 2012-07-07 14:07:35 +0200 |
| commit | cc009defa4211aa58b3387b59d568cf8ea863ef4 (patch) | |
| tree | 95088dc82bfd4a576d24c4b90205e3c285afe451 | |
| parent | b78375a806ed04eb22b963255cfdef8df702de47 (diff) | |
omap4: Use a smaller M,N couple for IVA DPLL
This reduced M,N couple corresponds to the advised value from
TI HW team.
Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.
Signed-off-by: Sebastien Jan <[email protected]>
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/clocks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index c568951a91a..1d92e665453 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ |