diff options
| author | Simon Glass <[email protected]> | 2015-08-22 15:58:53 -0600 |
|---|---|---|
| committer | Simon Glass <[email protected]> | 2015-08-26 07:54:14 -0700 |
| commit | cce7e0fa2b43b24b6a7553b348d3e716159f6c50 (patch) | |
| tree | 14a4ddf594616743460394df056150cf09f66335 | |
| parent | bccdf1de75708fe4138a00cc05d8fde8b35476ac (diff) | |
x86: minnowmax: Add access to GPIOs E0, E1, E2
These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.
Signed-off-by: Simon Glass <[email protected]>
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index f4e0a353f2b..a8ecf0d5f4b 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -30,6 +30,33 @@ compatible = "intel,x86-pinctrl"; io-base = <0x4c>; + /* GPIO E0 */ + soc_gpio_s5_0@0 { + gpio-offset = <0x80 0>; + pad-offset = <0x1d0>; + mode-gpio; + output-value = <0>; + direction = <PIN_OUTPUT>; + }; + + /* GPIO E1 */ + soc_gpio_s5_1@0 { + gpio-offset = <0x80 1>; + pad-offset = <0x210>; + mode-gpio; + output-value = <0>; + direction = <PIN_OUTPUT>; + }; + + /* GPIO E2 */ + soc_gpio_s5_2@0 { + gpio-offset = <0x80 2>; + pad-offset = <0x1e0>; + mode-gpio; + output-value = <0>; + direction = <PIN_OUTPUT>; + }; + pin_usb_host_en0@0 { gpio-offset = <0x80 8>; pad-offset = <0x260>; |