diff options
| author | Venkatesh Yadav Abbarapu <[email protected]> | 2025-07-04 09:34:44 +0530 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2025-07-08 14:58:44 +0200 |
| commit | cd9123507003e07b13e61d72e14e493bb338e827 (patch) | |
| tree | 4bc03778baefb32f29cf14bcf27824e3d2b30ea5 | |
| parent | 28fe6ea6e5744e008247ed5171ac25373e6863ce (diff) | |
spi: cadence_qspi: Fix odd byte write issue in STIG mode
Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG
mode for all ops with small payload") the utilization of STIG mode
has been implemented for read and write operations involving less
than 8 bytes of data.
However, following this commit, encountering timeout issues occurs when
writing odd bytes of data in DDR mode, as indicated below:
"jedec_spi_nor flash@0: flash operation timed out
SF: 3 bytes @ 0x0 Written: ERROR -110"
To resolve this issue, the number of bytes to write has been updated
specifically for DDR mode.
Signed-off-by: Tejas Bhumkar <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b579699d2eb..76569a8019b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -555,6 +555,9 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, u8 opcode; if (priv->dtr) + txlen += txlen & 1; + + if (priv->dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; |