diff options
| author | Jonas Karlman <[email protected]> | 2023-03-14 00:38:32 +0000 |
|---|---|---|
| committer | Kever Yang <[email protected]> | 2023-03-19 13:20:21 +0800 |
| commit | d11f0dac30215361aa046f593d003a7ea094e8a1 (patch) | |
| tree | 4854f66a0324e573f51bebb72b2cb170d2728c98 | |
| parent | 42a502ad1ae23b923dfcf8c5caa0aa727efd4062 (diff) | |
mmc: rockchip_dw_mmc: Fix get_mmc_clk return value
The get_mmc_clk ops is expected to set a clock rate and return the
configured rate as an unsigned value. However, if clk_set_rate fails,
e.g. using a fixed rate clock, a negative error value is returned.
The mmc core will treat this as a valid unsigned rate and tries to
configure a divider based on this bogus clock rate.
Use 0 as the return value when setting clock rate fails, the mmc core
will configure to use bypass mode instead of using a bogus divider.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
| -rw-r--r-- | drivers/mmc/rockchip_dw_mmc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 3661ce33143..72c820ee633 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { debug("%s: err=%d\n", __func__, ret); - return ret; + return 0; } return freq; |