stm32mp2: Update size of DDR entry in MMU table

On 1GB board, in particular cases, a prefetch operation is done just above
the 1GB boundary. The DDR size is 1GB (0x80000000 to 0xc0000000), there is
an access on 0xc00017c0 (ie 0x800017c0).

As beginning of DDR is protected by MMU until CONFIG_TEXT_BASE
(0x80000000 to 0x84000000), it triggers the following IAC:

E/TC:0   stm32_iac_itr:192 IAC exceptions [159:128]: 0x200
E/TC:0   stm32_iac_itr:197 IAC exception ID: 137
I/TC:

DUMPING DATA FOR risaf@420d0000
I/TC: =====================================================
I/TC: Status register (IAESR0): 0x11
I/TC: -----------------------------------------------------
I/TC: Faulty address (IADDR0): 0xc00017c0
I/TC: =====================================================
E/TC:0   Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-gitvalid.8>
E/TC:0   TEE load address @ 0x82000000
E/TC:0   Call stack:
E/TC:0    0x82007f30
E/TC:0    0x820444b4
E/TC:0    0x8202dc54
E/TC:0    0x82041fe0
E/TC:0    0x820143b8

By default, in MMU table, the DDR size is set to 4GB, but not all
STM32MP2 based board embeds 4GB, some has only 1 or 2GB of DDR.

The MMU table entry dedicated to DDR need to be updated with the real
DDR size previously read from DT.
After relocation, in enable_caches(), update the MMU table between the
dcache_disable() / dcache_enable() with the real DDR size.

Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>

1 files changed, 14 insertions, 0 deletions

diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
index a8a6bcf8ab4..178c6356b2b 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
@@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/armv8/mmu.h>
 #include <asm/system.h>
 #include <dm/device.h>
 #include <dm/lists.h>
@@ -70,8 +71,21 @@ int mach_cpu_init(void)
 
 void enable_caches(void)
 {
+	struct mm_region *mem = mem_map;
+
 	/* deactivate the data cache, early enabled in arch_cpu_init() */
 	dcache_disable();
+
+	/* Parse mem_map and find DDR entry */
+	while (mem->size) {
+		if (mem->phys == CONFIG_TEXT_BASE) {
+			/* update DDR entry with real DDR size */
+			mem->size = gd->ram_size;
+			break;
+		}
+		mem++;
+	}
+
 	/*
 	 * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
 	 * to update the TLB location udpated in board_f.c::reserve_mmu