diff options
| author | Jonas Karlman <[email protected]> | 2026-03-22 21:39:55 +0000 |
|---|---|---|
| committer | Stefan Roese <[email protected]> | 2026-06-09 11:51:19 +0200 |
| commit | d62801d09441acfebe2c8b7da66de70e6e5ad492 (patch) | |
| tree | b8eb43d840da249a5f7466e2dc3f3b7104868db0 | |
| parent | d98e11bcbcbde2d7448a30cec45d80a9215d3f98 (diff) | |
watchdog: designware: Fix probe when clk_enable return ENOSYS
Rockchip SoCs typically reset with all (or most) clocks ungated. Because
of this, U-Boot clock drivers for Rockchip typically do not implement
the optional clk-uclass enable/disable ops.
Normal driver model behavior is to return -ENOSYS when an uclass ops
is not implemented.
Ignore -ENOSYS to allow the designware watchdog driver to be probed on
platforms that do not implement the clk-uclass enable/disable ops, e.g.
Rockchip RK3308.
Signed-off-by: Jonas Karlman <[email protected]>
| -rw-r--r-- | drivers/watchdog/designware_wdt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index bd9d7105366..91228de5e8e 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -122,7 +122,7 @@ static int designware_wdt_probe(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret) + if (ret && ret != -ENOSYS) return ret; priv->clk_khz = clk_get_rate(&clk) / 1000; |