diff options
| author | Hrushikesh Salunke <[email protected]> | 2026-02-16 15:58:32 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-03-16 08:24:04 -0600 |
| commit | d83eefab8cfd58b8e4259734b2e19b30a8659461 (patch) | |
| tree | 574732bec602ca6b76afca52d4ba2891cc16d34a | |
| parent | 35e1083fb930ba1fa3a3c5cd139bf8285043c191 (diff) | |
configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot
J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The
PCIe1 instance is used for PCIe endpoint boot. Enable the configs
required for PCIe boot on the J784S4 platform.
Additionally, enable configs for J721E WIZ SERDES wrapper, Cadence
Torrent PHY, and MMIO multiplexer. These are required to configure
the SERDES lanes at the R5 SPL stage for PCIe endpoint operation.
Signed-off-by: Hrushikesh Salunke <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Udit Kumar <[email protected]>
| -rw-r--r-- | configs/j784s4_evm_r5_defconfig | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 25ab6f17d17..4462e7530e4 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -50,9 +50,16 @@ CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_PCI_ENDPOINT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_PCI_DFU=y +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x80800000 +CONFIG_SPL_PCI_DFU_BAR_SIZE=0x400000 +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x104c +CONFIG_SPL_PCI_DFU_DEVICE_ID=0xb012 +CONFIG_SPL_PCI_DFU_BOOT_PHASE="tiboot3.bin" # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -120,6 +127,12 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y +CONFIG_MULTIPLEXER=y +CONFIG_SPL_MUX_MMIO=y +CONFIG_PCIE_CDNS_TI_EP=y +CONFIG_SPL_PHY=y +CONFIG_SPL_PHY_CADENCE_TORRENT=y +CONFIG_SPL_PHY_J721E_WIZ=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y |