diff options
| author | Gautam Bhat <[email protected]> | 2017-07-03 00:50:32 +0530 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2017-07-12 09:44:22 +0200 |
| commit | d8fab10cb48e42c6ba84925af058349dca46dfa0 (patch) | |
| tree | 05d3ed80960169d360cca401e99e9fed6e4375f3 | |
| parent | a1d1fdc920cfb4c0126e5f8ff5233dd391548a0b (diff) | |
mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization.
This change sets the VLDO4 settings output to 2.8V in PMIC
initialization so that the MIPI DSI/CSI input voltage is 2.8V
as per the schematics. The original code provides an output of
3.3V which violates the voltage mentioned in the schematics.
Signed-off-by: Gautam Bhat <[email protected]>
Acked-by: Fabio Estevam <[email protected]>
| -rw-r--r-- | board/freescale/mx7dsabresd/mx7dsabresd.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index ecea5a529aa..7d22501d269 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -354,6 +354,12 @@ int power_init_board(void) pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + /* + * Set the voltage of VLDO4 output to 2.8V which feeds + * the MIPI DSI and MIPI CSI inputs. + */ + pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); + return 0; } #endif |