diff options
| author | Neha Malcom Francis <[email protected]> | 2026-04-15 20:51:51 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-05-11 12:32:00 -0600 |
| commit | d99cb46a2cc4d735aea125e315d6ee257077b516 (patch) | |
| tree | 221b7411a62fb624c3359a49d0f758d69abfa105 | |
| parent | ad681c816484c2246b4803de64553f760c0f44cd (diff) | |
arch: mach-k3: j721s2_init: Add workaround for errata i2437
Add the workaround proposed for J721S2 errata i2437 (link) for SE
clock-gating turning off too early. Without this, a hardware bug present
in C7120 leads to C7120 CPU hanging.
Link: https://www.ti.com/lit/pdf/sprz530
Signed-off-by: Neha Malcom Francis <[email protected]>
Signed-off-by: Udit Kumar <[email protected]>
| -rw-r--r-- | arch/arm/mach-k3/j721s2/j721s2_init.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index b5453d8895d..780d853423f 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -40,6 +40,15 @@ #define NB_THREADMAP_BIT1 BIT(1) #define NB_THREADMAP_BIT2 BIT(2) +/* + * RAT mapping for errata ID: i2437 + */ +#define RAT_ERRATA_2437_BASE_REGION0 0x40f90000 +#define RAT_ERRATA_2437_IN_ADDR 0xc0000000 +#define RAT_ERRATA_2437_OUT_ADDR_U 0x0000004d +#define RAT_ERRATA_2437_OUT_ADDR_L 0x21000000 +#define RAT_ERRATA_2437_CTRL 0x80000010 + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, @@ -346,6 +355,36 @@ void board_init_f(ulong dummy) if (ret) printf("AVS init failed: %d\n", ret); } + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Errata ID i2437: SE Clock-Gating Turning Off Too Early + * + * A hardware bug is present in the C7120 Streaming Engine top level + * clock gating logic that can lead to the C7120 CPU hanging. + + * Workaround: The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the + * COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the + * name of the specific C7120 core) must be enabled before power-up + * of the C7120 core to override all clock-gating. + */ + + /* Setup RAT mapping */ + debug("Errata i2437: Use RAT for COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register\n"); + writel_verify(RAT_ERRATA_2437_IN_ADDR, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_L, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_U, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + writel_verify(RAT_ERRATA_2437_CTRL, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + + /* Enable DSP_X_DEBUG_CLKEN_OVERRIDE for C71x cores */ + writel_verify(0x300, RAT_ERRATA_2437_IN_ADDR + 0x200); + + /* Clear RAT mapping */ + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + } } #endif |