diff options
| author | Peng Fan <[email protected]> | 2023-06-15 18:09:21 +0800 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2023-07-13 11:29:40 +0200 |
| commit | dc2d49209ea43a9b253bcf1f0dfcff6ea3d72405 (patch) | |
| tree | 9cd4011e8c276d2418c7e512ee32a35a15baab7f | |
| parent | e8cd1f60d9642d6e5bf346749481dcd1986d4fc2 (diff) | |
imx: imx8m: clock: not configure reserved SRC register
i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 31c34b6031f..986870799d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = &ana_pll->dram_pll_gnrl_ctl; break; |