diff options
| author | Tom Rini <[email protected]> | 2026-05-15 17:32:13 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-05-15 17:32:13 -0600 |
| commit | dc4dd589269d0c3fbaee6be41241b66d685686b2 (patch) | |
| tree | 5b7489ec0f9d6abc28466d06de30f32e424493b5 | |
| parent | a6f6947e43fba91de3ec5d0390eee7eb1a6a80f7 (diff) | |
| parent | 9e46861a01dd0a011616bf219f393303580dcd8b (diff) | |
Merge tag 'u-boot-imx-next-20260515' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30134
- Several conversions to OF_UPSTREAM.
- Added i.MX9 Quickboot support.
- Added support for i.MX952 in the fsl_enetc driver.
- Update i.MX91 part number detection.
58 files changed, 1018 insertions, 6582 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 0dcc7243124..b61cbb2f736 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -310,26 +310,13 @@ M: Fabio Estevam <[email protected]> R: NXP i.MX U-Boot Team <[email protected]> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-imx.git -F: arch/Kconfig.nxp +N: imx +N: mxc +N: nxp +N: vf610 F: arch/arm/cpu/arm1136/mx*/ F: arch/arm/cpu/arm926ejs/mx*/ -F: arch/arm/cpu/armv7/vf610/ -F: arch/arm/dts/*imx* -F: arch/arm/mach-imx/ -F: arch/arm/include/asm/arch-imx*/ F: arch/arm/include/asm/arch-mx*/ -F: arch/arm/include/asm/arch-vf610/ -F: arch/arm/include/asm/mach-imx/ -F: board/nxp/*mx*/ -F: board/nxp/common/ -F: common/spl/spl_imx_container.c -F: doc/board/nxp/ -F: doc/imx/ -F: drivers/mailbox/imx-mailbox.c -F: drivers/remoteproc/imx* -F: drivers/serial/serial_mxc.c -F: drivers/spi/nxp_xspi.c -F: include/imx_container.h ARM HISILICON M: Peter Griffin <[email protected]> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e79cfb4b633..0f4f6c986f0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -879,8 +879,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ imx8mq-cm.dtb \ - imx8mq-mnt-reform2.dtb \ - imx8mq-phanbell.dtb \ imx8mp-data-modul-edm-sbc.dtb \ imx8mp-dhcom-som-overlay-rev100.dtbo \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ @@ -890,10 +888,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ imx8mp-dhcom-picoitx.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ - imx8mp-msc-sm2s.dtb \ - imx8mq-pico-pi.dtb \ - imx8mq-kontron-pitx-imx8m.dtb \ - imx8mq-librem5-r4.dtb + imx8mp-msc-sm2s.dtb dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-frdm.dtb \ diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi deleted file mode 100644 index 03266bd90a0..00000000000 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ /dev/null @@ -1,437 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - leds { - compatible = "gpio-leds"; - - led0 { - label = "gen_led0"; - gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led1 { - label = "gen_led1"; - gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "gen_led2"; - gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led3>; - label = "heartbeat"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie0_refclk_gated: pcie0-refclk-gated { - compatible = "gpio-gate-clock"; - clocks = <&pcie0_refclk>; - #clock-cells = <0>; - enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg1: regulator-usbotg1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_otg1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_camera: regulator-camera { - compatible = "regulator-fixed"; - regulator-name = "mipi_pwr"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100000>; - }; - - reg_pcie0: regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "pci_pwr_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - }; -}; - -&csi { - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - eeprom@0 { - compatible = "microchip,at25160bn", "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pagesize = <32>; - size = <2048>; - address-width = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clk IMX8MM_CLK_CLKO1>; - clock-names = "xclk"; - assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; - assigned-clock-parents = <&clk IMX8MM_CLK_24M>; - assigned-clock-rates = <24000000>; - AVDD-supply = <®_camera>; /* 2.8v */ - powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&imx8mm_mipi_csi_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - pca6416_0: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6414>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - pca6416_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&mipi_csi { - status = "okay"; - ports { - port@0 { - imx8mm_mipi_csi_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk_gated>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk_gated>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - vpcie-supply = <®_pcie0>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MM_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usbotg1>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbphynop2 { - reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_led3: led3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 - >; - }; - - pinctrl_pcal6414: pcal6414-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 - >; - }; - - pinctrl_reg_usb_otg1: usbotg1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 - MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 - MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 - MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi deleted file mode 100644 index 9e82069c941..00000000000 --- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - leds { - compatible = "gpio-leds"; - - led-0 { - label = "gen_led0"; - gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - label = "gen_led1"; - gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "gen_led2"; - gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led3>; - label = "heartbeat"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "vsd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_otg>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - eeprom@0 { - compatible = "microchip,at25160bn", "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pagesize = <32>; - size = <2048>; - address-width = <16>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - pca6416_0: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6414>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - pca6416_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; -}; - -&easrc { - fsl,asrc-rate = <48000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MN_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg_vbus>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_led3: led3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 - >; - }; - - pinctrl_pcal6414: pcal6414-gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 - >; - }; - - pinctrl_reg_usb_otg: reg-otggrp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 - MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 - MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 - MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi deleted file mode 100644 index 261c3654007..00000000000 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include <dt-bindings/usb/pd.h> -#include "imx8mn.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "yellow:status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - linux,autosuspend-period = <125>; - }; - - audio_codec_bt_sco: audio-codec-bt-sco { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - clock-names = "mclk"; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai2>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&audio_codec_bt_sco 1>; - }; - }; - - sound-wm8524 { - compatible = "fsl,imx-audio-wm8524"; - model = "wm8524-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8524>; - audio-asrc = <&easrc>; - audio-routing = - "Line Out Jack", "LINEVOUTL", - "Line Out Jack", "LINEVOUTR"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif1>; - spdif-out; - spdif-in; - }; -}; - -&easrc { - fsl,asrc-rate = <48000>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - qca,disable-smarteee; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <166000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MN_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif1>; - assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MN_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_spdif1: spdif1grp { - fsl,pins = < - MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 - MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 - MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 - MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 - MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts deleted file mode 100644 index a91c136797f..00000000000 --- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts +++ /dev/null @@ -1,613 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree File for the Kontron pitx-imx8m board. - * - * Copyright (C) 2021 Heiko Thiery <[email protected]> - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include <dt-bindings/net/ti-dp83867.h> - -/ { - model = "Kontron pITX-imx8m"; - compatible = "kontron,pitx-imx8m", "fsl,imx8mq"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &qspi0; - spi1 = &ecspi2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - pcie0_refclk: pcie0-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie1_refclk: pcie1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - regulator-name = "V_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <20000>; - enable-active-high; - }; -}; - -&ecspi2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@0 { - compatible = "infineon,slb9670"; - reg = <0>; - spi-max-frequency = <43000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <280>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - fsl,pfuze-support-disable-sw; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-name = "V_0V9_GPU"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-name = "V_0V9_VPU"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-name = "V_1V1_NVCC_DRAM"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-name = "V_1V0_DRAM"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-name = "V_1V8_S0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-name = "NC"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-name = "V_0V9_SNVS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-name = "V_0V55_VREF_DDR"; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-name = "V_1V5_CSI"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-name = "V_0V9_PHY"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-name = "V_1V8_PHY"; - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-name = "V_1V8_VDDA"; - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-name = "V_3V3_PHY"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-name = "V_2V8_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - fan-controller@1b { - compatible = "maxim,max6650"; - reg = <0x1b>; - maxim,fan-microvolt = <5000000>; - }; - - rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - sensor@4b { - compatible = "national,lm75b"; - reg = <0x4b>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -/* M.2 B-key slot */ -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -/* Intel Ethernet Controller I210/I211 */ -&pcie1 { - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - fsl,max-link-speed = <1>; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - m25p,fast-read; - spi-max-frequency = <50000000>; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - assigned-clocks = <&clk IMX8MQ_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */ - MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */ - MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */ - MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */ - MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */ - MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */ - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */ - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */ - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */ - MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */ - >; - }; - - pinctrl_reg_usdhc2: regusdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 - MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 - MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 - MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 - >; - }; - - pinctrl_ecspi2_cs: ecspi2csgrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 - MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usb0: usb0grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19 - MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-librem5-r3.dtsi b/arch/arm/dts/imx8mq-librem5-r3.dtsi deleted file mode 100644 index e4f8b47cce4..00000000000 --- a/arch/arm/dts/imx8mq-librem5-r3.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2021 Purism SPC <[email protected]> - -/dts-v1/; - -/* - * This file describes hardware that is shared among r3 ("Dogwood") and - * later revisions of the Librem 5 so it has to be included in dts there. - */ - -#include "imx8mq-librem5.dtsi" - -/ { - model = "Purism Librem 5r3"; - compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; -}; - -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - -&camera_front { - pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>; - shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; -}; - -&iomuxc { - pinctrl_r3_camera_pwr: r3camerapwrgrp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83 - >; - }; -}; - -&proximity { - proximity-near-level = <25>; -}; diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts b/arch/arm/dts/imx8mq-librem5-r4.dts deleted file mode 100644 index 1056b7981bd..00000000000 --- a/arch/arm/dts/imx8mq-librem5-r4.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2021 Purism SPC <[email protected]> - -/dts-v1/; - -#include "imx8mq-librem5-r3.dtsi" - -/ { - model = "Purism Librem 5r4"; - compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; -}; - -&bat { - maxim,rsns-microohm = <1667>; -}; - -&led_backlight { - led-max-microamp = <25000>; -}; - -&lcd_panel { - compatible = "ys,ys57pss36bh5gq"; -}; - -&proximity { - proximity-near-level = <10>; -}; diff --git a/arch/arm/dts/imx8mq-librem5.dtsi b/arch/arm/dts/imx8mq-librem5.dtsi deleted file mode 100644 index ae08556b2ef..00000000000 --- a/arch/arm/dts/imx8mq-librem5.dtsi +++ /dev/null @@ -1,1382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2020 Purism SPC - */ - -/dts-v1/; - -#include "dt-bindings/input/input.h" -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/leds/common.h> -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/usb/pd.h" -#include "imx8mq.dtsi" - -/ { - model = "Purism Librem 5"; - compatible = "purism,librem5", "fsl,imx8mq"; - chassis-type = "handset"; - - backlight_dsi: backlight-dsi { - compatible = "led-backlight"; - leds = <&led_backlight>; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keys>; - - key-vol-down { - label = "VOL_DOWN"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <50>; - wakeup-source; - }; - - key-vol-up { - label = "VOL_UP"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <50>; - wakeup-source; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_BLUE>; - max-brightness = <248>; - pwms = <&pwm2 0 50000 0>; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - max-brightness = <248>; - pwms = <&pwm4 0 50000 0>; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - max-brightness = <248>; - pwms = <&pwm3 0 50000 0>; - }; - }; - - reg_aud_1v8: regulator-audio-1v8 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopwr>; - regulator-name = "AUDIO_PWR_EN"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* - * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC - * since we can't have it twice in the 2 different regulator nodes. - */ - reg_csi_1v8: regulator-csi-1v8 { - compatible = "regulator-fixed"; - regulator-name = "CAMERA_VDDIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_vdd_3v3>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* controlled by the CAMERA_POWER_KEY HKS */ - reg_vcam_1v2: regulator-vcam-1v2 { - compatible = "regulator-fixed"; - regulator-name = "CAMERA_VDDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <®_vdd_1v8>; - enable-active-high; - }; - - reg_vcam_2v8: regulator-vcam-2v8 { - compatible = "regulator-fixed"; - regulator-name = "CAMERA_VDDA_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <®_vdd_3v3>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_gnss: regulator-gnss { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gnsspwr>; - regulator-name = "GNSS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_hub: regulator-hub { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hub_pwr>; - regulator-name = "HUB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_1v8: regulator-lcd-1v8 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsien>; - regulator-name = "LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_vdd_1v8>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* Otherwise i2c3 is not functional */ - regulator-always-on; - }; - - reg_lcd_3v4: regulator-lcd-3v4 { - compatible = "regulator-fixed"; - regulator-name = "LCD_3V4"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsibiasen>; - vin-supply = <®_vsys_3v4>; - gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vdd_sen: regulator-vdd-sen { - compatible = "regulator-fixed"; - regulator-name = "VDD_SEN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vdd_1v8: regulator-vdd-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&buck7_reg>; - }; - - reg_vdd_3v3: regulator-vdd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vsys_3v4: regulator-vsys-3v4 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V4"; - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - regulator-always-on; - }; - - reg_wifi_3v3: regulator-wifi-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr>; - regulator-name = "3V3_WIFI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vdd_3v3>; - }; - - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - simple-audio-card,name = "Librem 5"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Headphone", "Headphones", - "Microphone", "Headset Mic", - "Microphone", "Digital Mic", - "Speaker", "Speaker"; - simple-audio-card,routing = - "Headphones", "HPOUTL", - "Headphones", "HPOUTR", - "Speaker", "SPKOUTL", - "Speaker", "SPKOUTR", - "Headset Mic", "MICBIAS", - "IN3R", "Headset Mic", - "DMICDAT", "Digital Mic"; - simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - frame-master; - bitclock-master; - }; - }; - - sound-wwan { - compatible = "simple-audio-card"; - simple-audio-card,name = "Modem"; - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sai6>; - frame-inversion; - }; - - simple-audio-card,codec { - sound-dai = <&bm818_codec>; - frame-master; - bitclock-master; - }; - }; - - usdhc2_pwrseq: pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt>, <&pinctrl_wifi_disable>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>, - <&gpio4 29 GPIO_ACTIVE_HIGH>; - }; - - bm818_codec: sound-wwan-codec { - compatible = "broadmobi,bm818", "option,gtm601"; - #sound-dai-cells = <0>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm1 0 1000000000 0>; - pwm-names = "enable"; - vcc-supply = <®_vdd_3v3>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&csi1 { - status = "okay"; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - status = "okay"; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&dphy { - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - nor_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "protected0"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "firmware"; - reg = <0x30000 0x1d0000>; - read-only; - }; - }; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_5v>; - - pmic-5v-hog { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - input; - lane-mapping = "pmic-5v"; - }; -}; - -&iomuxc { - pinctrl_audiopwr: audiopwrgrp { - fsl,pins = < - /* AUDIO_POWER_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 - >; - }; - - pinctrl_bl: blgrp { - fsl,pins = < - /* BACKLINGE_EN */ - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 - >; - }; - - pinctrl_bt: btgrp { - fsl,pins = < - /* BT_REG_ON */ - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x83 - >; - }; - - pinctrl_camera_pwr: camerapwrgrp { - fsl,pins = < - /* CAMERA_PWR_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 - >; - }; - - pinctrl_csi1: csi1grp { - fsl,pins = < - /* CSI1_NRST */ - MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 - >; - }; - - pinctrl_charger_in: chargeringrp { - fsl,pins = < - /* CHRG_INT */ - MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 - >; - }; - - pinctrl_dsibiasen: dsibiasengrp { - fsl,pins = < - /* DSI_BIAS_EN */ - MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 - >; - }; - - pinctrl_dsien: dsiengrp { - fsl,pins = < - /* DSI_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 - >; - }; - - pinctrl_dsirst: dsirstgrp { - fsl,pins = < - /* DSI_RST */ - MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x83 - /* DSI_TE */ - MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x83 - /* TP_RST */ - MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x83 - >; - }; - - pinctrl_ecspi1: ecspigrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 - MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 - >; - }; - - pinctrl_gauge: gaugegrp { - fsl,pins = < - /* BAT_LOW */ - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 - >; - }; - - pinctrl_gnsspwr: gnsspwrgrp { - fsl,pins = < - /* GPS3V3_EN */ - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 - >; - }; - - pinctrl_haptic: hapticgrp { - fsl,pins = < - /* MOTO */ - MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - /* HEADPHONE_DET_1V8 */ - MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 - >; - }; - - pinctrl_hub_pwr: hubpwrgrp { - fsl,pins = < - /* HUB_PWR_3V3_EN */ - MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 - >; - }; - - pinctrl_keys: keysgrp { - fsl,pins = < - /* VOL- */ - MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 - /* VOL+ */ - MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 - >; - }; - - pinctrl_led_b: ledbgrp { - fsl,pins = < - /* LED_B */ - MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 - >; - }; - - pinctrl_led_g: ledggrp { - fsl,pins = < - /* LED_G */ - MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 - >; - }; - - pinctrl_led_r: ledrgrp { - fsl,pins = < - /* LED_R */ - MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 - >; - }; - - pinctrl_mag: maggrp { - fsl,pins = < - /* INT_MAG */ - MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC_NINT */ - MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 - >; - }; - - pinctrl_pmic_5v: pmic5vgrp { - fsl,pins = < - /* PMIC_5V */ - MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 - >; - }; - - pinctrl_prox: proxgrp { - fsl,pins = < - /* INT_LIGHT */ - MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - /* RTC_INT */ - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - >; - }; - - pinctrl_sai6: sai6grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 - >; - }; - - pinctrl_tcpc: tcpcgrp { - fsl,pins = < - /* TCPC_INT */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - /* TP_INT */ - MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x80 - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - /* TYPEC_MUX_EN */ - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 - MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 - MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_wifi_disable: wifidisablegrp { - fsl,pins = < - /* WIFI_REG_ON */ - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x83 - >; - }; - - pinctrl_wifi_pwr: wifipwrgrp { - fsl,pins = < - /* WIFI3V3_EN */ - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x83 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - /* nWDOG */ - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f - >; - }; -}; - -&i2c1 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - typec_pd: usb-pd@3f { - compatible = "ti,tps6598x"; - reg = <0x3f>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_con_hs: endpoint { - remote-endpoint = <&typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usb_con_ss: endpoint { - remote-endpoint = <&typec_ss>; - }; - }; - }; - }; - }; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck4_reg: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - /* VDD_PHY_0V9 - MIPI and HDMI domains */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - /* VDD_PHY_3V3 - USB domain */ - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - magnetometer@1e { - compatible = "st,lsm9ds1-magn"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mag>; - interrupt-parent = <&gpio3>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - vdd-supply = <®_vdd_sen>; - vddio-supply = <®_vdd_1v8>; - }; - - regulator@3e { - compatible = "tps65132"; - reg = <0x3e>; - - reg_lcd_avdd: outp { - regulator-name = "LCD_AVDD"; - vin-supply = <®_lcd_3v4>; - }; - - reg_lcd_avee: outn { - regulator-name = "LCD_AVEE"; - vin-supply = <®_lcd_3v4>; - }; - }; - - proximity: prox@60 { - compatible = "vishay,vcnl4040"; - reg = <0x60>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_prox>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - }; - - accel_gyro: accel-gyro@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - vdd-supply = <®_vdd_sen>; - vddio-supply = <®_vdd_1v8>; - }; -}; - -&i2c3 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - #sound-dai-cells = <0>; - mic-cfg = <0x200>; - DCVDD-supply = <®_aud_1v8>; - DBVDD-supply = <®_aud_1v8>; - AVDD-supply = <®_aud_1v8>; - CPVDD-supply = <®_aud_1v8>; - MICVDD-supply = <®_aud_1v8>; - PLLVDD-supply = <®_aud_1v8>; - SPKVDD1-supply = <®_vsys_3v4>; - SPKVDD2-supply = <®_vsys_3v4>; - gpio-cfg = < - 0x0000 /* n/c */ - 0x0001 /* gpio2, 1: default */ - 0x0013 /* gpio3, 2: dmicclk */ - 0x0000 /* n/c, 3: default */ - 0x8014 /* gpio5, 4: dmic_dat */ - 0x0000 /* gpio6, 5: default */ - >; - }; - - camera_front: camera@20 { - compatible = "hynix,hi846"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi1>; - clocks = <&clk IMX8MQ_CLK_CLKO2>; - assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; - assigned-clock-rates = <25000000>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - vdda-supply = <®_vcam_2v8>; - vddd-supply = <®_vcam_1v2>; - vddio-supply = <®_csi_1v8>; - rotation = <90>; - orientation = <0>; - - port { - camera1_ep: endpoint { - data-lanes = <1 2>; - link-frequencies = /bits/ 64 - <80000000 200000000 300000000>; - remote-endpoint = <&mipi1_sensor_ep>; - }; - }; - }; - - backlight@36 { - compatible = "ti,lm36922"; - reg = <0x36>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bl>; - #address-cells = <1>; - #size-cells = <0>; - enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - vled-supply = <®_vsys_3v4>; - ti,ovp-microvolt = <25000000>; - - led_backlight: led@0 { - reg = <0>; - label = ":backlight"; - linux,default-trigger = "backlight"; - led-max-microamp = <20000>; - }; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5506"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1440>; - vcc-supply = <®_lcd_1v8>; - }; -}; - -&i2c4 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - vcm@c { - compatible = "dongwoon,dw9714"; - reg = <0x0c>; - vcc-supply = <®_csi_1v8>; - }; - - bat: fuel-gauge@36 { - compatible = "maxim,max17055"; - reg = <0x36>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gauge>; - power-supplies = <&bq25895>; - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - maxim,rsns-microohm = <5000>; - }; - - bq25895: charger@6a { - compatible = "ti,bq25895", "ti,bq25890"; - reg = <0x6a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_in>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - phys = <&usb3_phy0>; - ti,precharge-current = <130000>; /* uA */ - ti,minimum-sys-voltage = <3700000>; /* uV */ - ti,boost-voltage = <5000000>; /* uV */ - ti,boost-max-current = <1500000>; /* uA */ - ti,use-vinmin-threshold = <1>; /* enable VINDPM */ - ti,vinmin-threshold = <3900000>; /* uV */ - monitored-battery = <&bat>; - power-supplies = <&typec_pd>; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_csi1 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - - mipi1_sensor_ep: endpoint { - remote-endpoint = <&camera1_ep>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&mipi_dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - lcd_panel: panel@0 { - compatible = "mantix,mlaf057we51-x"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsirst>; - avdd-supply = <®_lcd_avdd>; - avee-supply = <®_lcd_avee>; - vddi-supply = <®_lcd_1v8>; - backlight = <&backlight_dsi>; - reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - mantix,tp-rstn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pgc_gpu { - power-supply = <&buck3_reg>; -}; - -&pgc_mipi { - power-supply = <&ldo5_reg>; -}; - -&pgc_vpu { - power-supply = <&buck4_reg>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_haptic>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_b>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_r>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_g>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&sai6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai6>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-synchronous-rx; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { /* TPS - GPS - DEBUG */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - - gnss { - compatible = "globaltop,pa6h"; - vcc-supply = <®_gnss>; - current-speed = <9600>; - }; -}; - -&uart3 { /* SMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_hub>; - status = "okay"; -}; - -&usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - usb-role-switch; - status = "okay"; - - port@0 { - reg = <0>; - - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; - - port@1 { - reg = <1>; - - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip USB2642 */ - hub@1 { - compatible = "usb424,2640"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mass-storage@1 { - compatible = "usb424,4041"; - reg = <1>; - }; - }; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - vmmc-supply = <®_vdd_3v3>; - power-supply = <®_vdd_1v8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_wifi_3v3>; - mmc-pwrseq = <&usdhc2_pwrseq>; - post-power-on-delay-ms = <1000>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - max-frequency = <50000000>; - disable-wp; - cap-sdio-irq; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi index 46a4dfe4e8a..71ce1b5b3ca 100644 --- a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi @@ -9,3 +9,7 @@ &uart1 { /* console */ bootph-pre-ram; }; + +&{/panel} { + compatible = "innolux,n125hce-gn1", "simple-panel"; +}; diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts deleted file mode 100644 index 055031bba8c..00000000000 --- a/arch/arm/dts/imx8mq-mnt-reform2.dts +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/* - * Copyright 2019-2021 MNT Research GmbH - * Copyright 2021 Lucas Stach <[email protected]> - */ - -/dts-v1/; - -#include "imx8mq-nitrogen-som.dtsi" - -/ { - model = "MNT Reform 2"; - compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; - chassis-type = "laptop"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 10000 0>; - power-supply = <®_main_usb>; - enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - brightness-levels = <0 32 64 128 160 200 255>; - default-brightness-level = <6>; - }; - - panel { - compatible = "innolux,n125hce-gn1", "simple-panel"; - power-supply = <®_main_3v3>; - backlight = <&backlight>; - no-hpd; - - port { - panel_in: endpoint { - remote-endpoint = <&edp_bridge_out>; - }; - }; - }; - - pcie1_refclk: clock-pcie1-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_main_5v: regulator-main-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_main_3v3: regulator-main-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_main_usb: regulator-main-usb { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_main_5v>; - }; - - reg_main_1v8: regulator-main-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_main_3v3>; - }; - - reg_main_1v2: regulator-main-1v2 { - compatible = "regulator-fixed"; - regulator-name = "1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <®_main_5v>; - }; - - sound { - compatible = "fsl,imx-audio-wm8960"; - audio-cpu = <&sai2>; - audio-codec = <&wm8960>; - audio-routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT1", "Mic Jack", - "Mic Jack", "MICB", - "LINPUT2", "Line In Jack", - "RINPUT2", "Line In Jack"; - model = "wm8960-audio"; - }; -}; - -&dphy { - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; - assigned-clock-rates = <25000000>; - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - wm8960: codec@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <400000>; - status = "okay"; - - edp_bridge: bridge@2c { - compatible = "ti,sn65dsi86"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edp_bridge>; - reg = <0x2c>; - enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - vccio-supply = <®_main_1v8>; - vpll-supply = <®_main_1v8>; - vcca-supply = <®_main_1v2>; - vcc-supply = <®_main_1v2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - edp_bridge_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - - port@1 { - reg = <1>; - - edp_bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -}; - -&lcdif { - assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; - /delete-property/assigned-clock-rates; - status = "okay"; -}; - -&mipi_dsi { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - mipi_dsi_out: endpoint { - remote-endpoint = <&edp_bridge_in>; - }; - }; - }; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -®_1p8v { - vin-supply = <®_main_5v>; -}; - -®_snvs { - vin-supply = <®_main_5v>; -}; - -®_arm_dram { - vin-supply = <®_main_5v>; -}; - -®_dram_1p1v { - vin-supply = <®_main_5v>; -}; - -®_soc_gpu_vpu { - vin-supply = <®_main_5v>; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - assigned-clock-rates = <25000000>; - fsl,sai-mclk-direction-output; - fsl,sai-asynchronous; - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usb3_phy0 { - vbus-supply = <®_main_usb>; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_main_usb>; - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_main_3v3>; - vmmc-supply = <®_main_3v3>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3 - >; - }; - - pinctrl_edp_bridge: edpbridgegrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022 - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022 - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022 - >; - }; - - pinctrl_pcie1: pcie1grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-nitrogen-som.dtsi b/arch/arm/dts/imx8mq-nitrogen-som.dtsi deleted file mode 100644 index 395f77b5aca..00000000000 --- a/arch/arm/dts/imx8mq-nitrogen-som.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 Boundary Devices - * Copyright 2021 Lucas Stach <[email protected]> - */ - -#include "imx8mq.dtsi" - -/ { - model = "Boundary Devices i.MX8MQ Nitrogen8M"; - compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - reg_1p8v: regulator-fixed-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_snvs: regulator-fixed-snvs { - compatible = "regulator-fixed"; - regulator-name = "VDD_SNVS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&{/opp-table/opp-800000000} { - opp-microvolt = <1000000>; -}; - -&{/opp-table/opp-1000000000} { - opp-microvolt = <1000000>; -}; - -&A53_0 { - cpu-supply = <®_arm_dram>; -}; - -&A53_1 { - cpu-supply = <®_arm_dram>; -}; - -&A53_2 { - cpu-supply = <®_arm_dram>; -}; - -&A53_3 { - cpu-supply = <®_arm_dram>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9546"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_pca9546>; - reg = <0x70>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - - i2c1a: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - reg_arm_dram: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - regulator-name = "VDD_ARM_DRAM_1V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - - i2c1b: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - reg_dram_1p1v: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - regulator-name = "NVCC_DRAM_1P1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - }; - - i2c1c: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - reg_soc_gpu_vpu: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - regulator-name = "VDD_SOC_GPU_VPU"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - }; - }; - - i2c1d: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&pgc_gpu { - power-supply = <®_soc_gpu_vpu>; -}; - -&pgc_vpu { - power-supply = <®_soc_gpu_vpu>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_snvs>; - bus-width = <8>; - non-removable; - no-mmc-hs400; - no-sdio; - no-sd; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022 - >; - }; - - pinctrl_i2c1_pca9546: i2c1-pca9546grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-phanbell.dts b/arch/arm/dts/imx8mq-phanbell.dts deleted file mode 100644 index a3b9d615a3b..00000000000 --- a/arch/arm/dts/imx8mq-phanbell.dts +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017-2019 NXP - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "Google i.MX8MQ Phanbell"; - compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x40000000>; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - fan: gpio-fan { - compatible = "gpio-fan"; - gpio-fan,speed-map = <0 0 8600 1>; - gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - #cooling-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_fan>; - status = "okay"; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&cpu_thermal { - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: trip1 { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip3 { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - - fan_toggle0: trip4 { - temperature = <65000>; - hysteresis = <10000>; - type = "active"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A53_0 0 1>; /* Exclude highest OPP */ - }; - - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&A53_0 0 2>; /* Exclude two highest OPPs */ - }; - - map4 { - trip = <&fan_toggle0>; - cooling-device = <&fan 0 1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - #clock-cells = <0>; - clocks = <&pmic_osc>; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <900000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_gpio_fan: gpiofangrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-pico-pi.dts b/arch/arm/dts/imx8mq-pico-pi.dts deleted file mode 100644 index 89cbec5c41b..00000000000 --- a/arch/arm/dts/imx8mq-pico-pi.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 Wandboard, Org. - * Copyright 2017 NXP - * - * Author: Richard Hu <[email protected]> - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "TechNexion PICO-PI-8M"; - compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 14 GPIO_ACTIVE_LOW>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - reg = <0x4b>; - compatible = "rohm,bd71837"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_otg_vbus: otgvbusgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */ - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi deleted file mode 100644 index 19eaa523564..00000000000 --- a/arch/arm/dts/imx8mq.dtsi +++ /dev/null @@ -1,1615 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <[email protected]> - */ - -#include <dt-bindings/clock/imx8mq-clock.h> -#include <dt-bindings/power/imx8mq-power.h> -#include <dt-bindings/reset/imx8mq-reset.h> -#include <dt-bindings/gpio/gpio.h> -#include "dt-bindings/input/input.h" -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/interconnect/imx8mq.h> -#include "imx8mq-pinfunc.h" - -/ { - interrupt-parent = <&gpc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc_25m: clock-osc-25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc_25m"; - }; - - osc_27m: clock-osc-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "osc_27m"; - }; - - hdmi_phy_27m: clock-hdmi-phy-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "hdmi_phy_27m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext4"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <900000>; - /* Industrial only */ - opp-supported-hw = <0xf>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <900000>; - /* Consumer only */ - opp-supported-hw = <0xe>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0xc>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x8>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu_alert: gpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ - interrupt-parent = <&gic>; - arm,no-tick-in-suspend; - }; - - soc: soc@0 { - compatible = "fsl,imx8mq-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; - nvmem-cells = <&imx8mq_uid>; - nvmem-cell-names = "soc_unique_id"; - - aips1: bus@30000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30000000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30000000 0x30000000 0x400000>; - - sai1: sai@30010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, - <&clk IMX8MQ_CLK_SAI1_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai6: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, - <&clk IMX8MQ_CLK_SAI6_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai5: sai@30040000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30040000 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, - <&clk IMX8MQ_CLK_SAI5_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai4: sai@30050000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, - <&clk IMX8MQ_CLK_SAI4_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 87 32>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - tmu: tmu@30260000 { - compatible = "fsl,imx8mq-tmu"; - reg = <0x30260000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; - little-endian; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023>, - <0x00000001 0x00000029>, - <0x00000002 0x0000002f>, - <0x00000003 0x00000035>, - <0x00000004 0x0000003d>, - <0x00000005 0x00000043>, - <0x00000006 0x0000004b>, - <0x00000007 0x00000051>, - <0x00000008 0x00000057>, - <0x00000009 0x0000005f>, - <0x0000000a 0x00000067>, - <0x0000000b 0x0000006f>, - - <0x00010000 0x0000001b>, - <0x00010001 0x00000023>, - <0x00010002 0x0000002b>, - <0x00010003 0x00000033>, - <0x00010004 0x0000003b>, - <0x00010005 0x00000043>, - <0x00010006 0x0000004b>, - <0x00010007 0x00000055>, - <0x00010008 0x0000005d>, - <0x00010009 0x00000067>, - <0x0001000a 0x00000070>, - - <0x00020000 0x00000017>, - <0x00020001 0x00000023>, - <0x00020002 0x0000002d>, - <0x00020003 0x00000037>, - <0x00020004 0x00000041>, - <0x00020005 0x0000004b>, - <0x00020006 0x00000057>, - <0x00020007 0x00000063>, - <0x00020008 0x0000006f>, - - <0x00030000 0x00000015>, - <0x00030001 0x00000021>, - <0x00030002 0x0000002d>, - <0x00030003 0x00000039>, - <0x00030004 0x00000045>, - <0x00030005 0x00000053>, - <0x00030006 0x0000005f>, - <0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, - <&clk IMX8MQ_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - lcdif: lcd-controller@30320000 { - compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; - reg = <0x30320000 0x10000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "pix"; - assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>, - <&clk IMX8MQ_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, - <&clk IMX8MQ_VIDEO_PLL1>, - <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <0>, <0>, <0>, <594000000>; - status = "disabled"; - - port { - lcdif_mipi_dsi: endpoint { - remote-endpoint = <&mipi_dsi_lcdif_in>; - }; - }; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - iomuxc_gpr: syscon@30340000 { - compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", - "syscon", "simple-mfd"; - reg = <0x30340000 0x10000>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ - }; - }; - - ocotp: efuse@30350000 { - compatible = "fsl,imx8mq-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; - #address-cells = <1>; - #size-cells = <1>; - - imx8mq_uid: soc-uid@410 { - reg = <0x4 0x8>; - }; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - - fec_mac_address: mac-address@90 { - reg = <0x90 6>; - }; - }; - - anatop: syscon@30360000 { - compatible = "fsl,imx8mq-anatop", "syscon"; - reg = <0x30360000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp{ - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; - offset = <0x34>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; - clock-names = "snvs-pwrkey"; - linux,keycode = <KEY_POWER>; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mq-ccm"; - reg = <0x30380000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - clocks = <&ckil>, <&osc_25m>, <&osc_27m>, - <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "ckil", "osc_25m", "osc_27m", - "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, - <&clk IMX8MQ_CLK_A53_CORE>, - <&clk IMX8MQ_CLK_NOC>, - <&clk IMX8MQ_CLK_AUDIO_AHB>, - <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, - <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, - <&clk IMX8MQ_AUDIO_PLL1>, - <&clk IMX8MQ_AUDIO_PLL2>; - assigned-clock-rates = <0>, <0>, - <800000000>, - <0>, - <0>, - <0>, - <786432000>, - <722534400>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_ARM_PLL_OUT>, - <0>, - <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_AUDIO_PLL1>, - <&clk IMX8MQ_AUDIO_PLL2>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx8mq-gpc"; - reg = <0x303a0000 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <3>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_mipi: power-domain@0 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_MIPI>; - }; - - /* - * As per comment in ATF source code: - * - * PCIE1 and PCIE2 share the - * same reset signal, if we - * power down PCIE2, PCIE1 - * will be held in reset too. - * - * So instead of creating two - * separate power domains for - * PCIE1 and PCIE2 we create a - * link between both and use - * it as a shared PCIE power - * domain. - */ - pgc_pcie: power-domain@1 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_PCIE1>; - power-domains = <&pgc_pcie2>; - }; - - pgc_otg1: power-domain@2 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; - }; - - pgc_otg2: power-domain@3 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; - }; - - pgc_ddr1: power-domain@4 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_DDR1>; - }; - - pgc_gpu: power-domain@5 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_GPU>; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - }; - - pgc_vpu: power-domain@6 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_VPU>; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, - <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, - <600000000>, - <800000000>, - <0>; - }; - - pgc_disp: power-domain@7 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_DISP>; - }; - - pgc_mipi_csi1: power-domain@8 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; - }; - - pgc_mipi_csi2: power-domain@9 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; - }; - - pgc_pcie2: power-domain@a { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_PCIE2>; - }; - }; - }; - }; - - aips2: bus@30400000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30400000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30400000 0x30400000 0x400000>; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, - <&clk IMX8MQ_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, - <&clk IMX8MQ_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, - <&clk IMX8MQ_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, - <&clk IMX8MQ_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc_25m>; - clock-names = "per"; - }; - }; - - aips3: bus@30800000 { /* AIPS3 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30800000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>, - <0x08000000 0x08000000 0x10000000>; - - spdif1: spdif@30810000 { - compatible = "fsl,imx35-spdif"; - reg = <0x30810000 0x10000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ - <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ - <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ - <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ - <&clk IMX8MQ_CLK_DUMMY>; /* spba */ - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, - <&clk IMX8MQ_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, - <&clk IMX8MQ_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, - <&clk IMX8MQ_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, - <&clk IMX8MQ_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, - <&clk IMX8MQ_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, - <&clk IMX8MQ_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - spdif2: spdif@308a0000 { - compatible = "fsl,imx35-spdif"; - reg = <0x308a0000 0x10000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ - <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ - <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ - <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ - <&clk IMX8MQ_CLK_DUMMY>; /* spba */ - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308b0000 0x10000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, - <&clk IMX8MQ_CLK_SAI2_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308c0000 0x10000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, - <&clk IMX8MQ_CLK_SAI3_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_AHB>, - <&clk IMX8MQ_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - mipi_dsi: mipi-dsi@30a00000 { - compatible = "fsl,imx8mq-nwl-dsi"; - reg = <0x30a00000 0x300>; - clocks = <&clk IMX8MQ_CLK_DSI_CORE>, - <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>, - <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_CORE>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, - <&clk IMX8MQ_SYS1_PLL_266M>; - assigned-clock-rates = <80000000>, <266000000>, <20000000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - mux-controls = <&mux 0>; - power-domains = <&pgc_mipi>; - phys = <&dphy>; - phy-names = "dphy"; - resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, - <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, - <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, - <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; - reset-names = "byte", "dpi", "esc", "pclk"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_dsi_lcdif_in: endpoint@0 { - reg = <0>; - remote-endpoint = <&lcdif_mipi_dsi>; - }; - }; - }; - }; - - dphy: dphy@30a00300 { - compatible = "fsl,imx8mq-mipi-dphy"; - reg = <0x30a00300 0x100>; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, - <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, - <&clk IMX8MQ_VIDEO_PLL1>, - <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; - #phy-cells = <0>; - power-domains = <&pgc_mipi>; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, - <&clk IMX8MQ_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - mipi_csi1: csi@30a70000 { - compatible = "fsl,imx8mq-mipi-csi2"; - reg = <0x30a70000 0x1000>; - clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, - <&clk IMX8MQ_CLK_CSI1_ESC>, - <&clk IMX8MQ_CLK_CSI1_PHY_REF>; - clock-names = "core", "esc", "ui"; - assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, - <&clk IMX8MQ_CLK_CSI1_PHY_REF>, - <&clk IMX8MQ_CLK_CSI1_ESC>; - assigned-clock-rates = <266000000>, <333000000>, <66000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_1000M>, - <&clk IMX8MQ_SYS1_PLL_800M>; - power-domains = <&pgc_mipi_csi1>; - resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; - fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; - interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; - interconnect-names = "dram"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - csi1_mipi_ep: endpoint { - remote-endpoint = <&csi1_ep>; - }; - }; - }; - }; - - csi1: csi@30a90000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; - reg = <0x30a90000 0x10000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; - clock-names = "mclk"; - status = "disabled"; - - port { - csi1_ep: endpoint { - remote-endpoint = <&csi1_mipi_ep>; - }; - }; - }; - - mipi_csi2: csi@30b60000 { - compatible = "fsl,imx8mq-mipi-csi2"; - reg = <0x30b60000 0x1000>; - clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, - <&clk IMX8MQ_CLK_CSI2_ESC>, - <&clk IMX8MQ_CLK_CSI2_PHY_REF>; - clock-names = "core", "esc", "ui"; - assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, - <&clk IMX8MQ_CLK_CSI2_PHY_REF>, - <&clk IMX8MQ_CLK_CSI2_ESC>; - assigned-clock-rates = <266000000>, <333000000>, <66000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_1000M>, - <&clk IMX8MQ_SYS1_PLL_800M>; - power-domains = <&pgc_mipi_csi2>; - resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; - fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; - interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; - interconnect-names = "dram"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - csi2_mipi_ep: endpoint { - remote-endpoint = <&csi2_ep>; - }; - }; - }; - }; - - csi2: csi@30b80000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; - reg = <0x30b80000 0x10000>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; - clock-names = "mclk"; - status = "disabled"; - - port { - csi2_ep: endpoint { - remote-endpoint = <&csi2_mipi_ep>; - }; - }; - }; - - mu: mailbox@30aa0000 { - compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_MU_ROOT>; - #mbox-cells = <2>; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - qspi0: spi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; - reg = <0x30bb0000 0x10000>, - <0x08000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, - <&clk IMX8MQ_CLK_QSPI_ROOT>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, - <&clk IMX8MQ_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET_TIMER>, - <&clk IMX8MQ_CLK_ENET_REF>, - <&clk IMX8MQ_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, - <&clk IMX8MQ_CLK_ENET_TIMER>, - <&clk IMX8MQ_CLK_ENET_REF>, - <&clk IMX8MQ_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS2_PLL_125M>, - <&clk IMX8MQ_SYS2_PLL_50M>; - assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - nvmem-cells = <&fec_mac_address>; - nvmem-cell-names = "mac-address"; - fsl,stop-mode = <&iomuxc_gpr 0x10 3>; - status = "disabled"; - }; - }; - - noc: interconnect@32700000 { - compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; - reg = <0x32700000 0x100000>; - clocks = <&clk IMX8MQ_CLK_NOC>; - fsl,ddrc = <&ddrc>; - #interconnect-cells = <1>; - operating-points-v2 = <&noc_opp_table>; - - noc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-133M { - opp-hz = /bits/ 64 <133333333>; - }; - - opp-400M { - opp-hz = /bits/ 64 <400000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; - }; - - aips4: bus@32c00000 { /* AIPS4 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - - irqsteer: interrupt-controller@32e2d000 { - compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; - reg = <0x32e2d000 0x1000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; - clock-names = "ipg"; - fsl,channel = <0>; - fsl,num-irqs = <64>; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - gpu: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x40000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - clock-names = "core", "shader", "bus", "reg"; - #cooling-cells = <2>; - assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, - <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>, - <&clk IMX8MQ_GPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL>; - assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>, <0>; - power-domains = <&pgc_gpu>; - }; - - usb_dwc3_0: usb@38100000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy0>, <&usb3_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg1>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy0: usb-phy@381f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x381f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_dwc3_1: usb@38200000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg2>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy1: usb-phy@382f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x382f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - vpu_g1: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu-g1"; - reg = <0x38300000 0x10000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; - }; - - vpu_g2: video-codec@38310000 { - compatible = "nxp,imx8mq-vpu-g2"; - reg = <0x38310000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; - }; - - vpu_blk_ctrl: blk-ctrl@38320000 { - compatible = "fsl,imx8mq-vpu-blk-ctrl"; - reg = <0x38320000 0x100>; - power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; - power-domain-names = "bus", "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - clock-names = "g1", "g2"; - #power-domain-cells = <1>; - }; - - pcie0: pcie@33800000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33800000 0x400000>, - <0x1ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - linux,pci-domain = <0>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <250000000>, <100000000>, - <10000000>; - status = "disabled"; - }; - - pcie1: pcie@33c00000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33c00000 0x400000>, - <0x27f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - linux,pci-domain = <1>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY2>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <250000000>, <100000000>, - <10000000>; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>, /* GICR */ - <0x31000000 0x2000>, /* GICC */ - <0x31010000 0x2000>, /* GICV */ - <0x31020000 0x2000>; /* GICH */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, - <&clk IMX8MQ_DRAM_PLL_OUT>, - <&clk IMX8MQ_CLK_DRAM_ALT>, - <&clk IMX8MQ_CLK_DRAM_APB>; - status = "disabled"; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; diff --git a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi index 97ce7402e50..24952579a67 100644 --- a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi +++ b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi @@ -10,7 +10,6 @@ }; &gpio1 { - reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; bootph-pre-ram; }; diff --git a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi index 83802156d52..45633765c0f 100644 --- a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi @@ -26,7 +26,6 @@ }; &gpio1 { - reg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>; bootph-pre-ram; ctrl-sleep-moci-hog { diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index a8e3f7354c7..bba12369f06 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2022 NXP + * Copyright 2022-2026 NXP */ #ifndef __ASM_ARCH_IMX8M_DDR_H @@ -100,6 +100,52 @@ struct dram_timing_info { extern struct dram_timing_info dram_timing; +/* Quick Boot related */ +#define DDRPHY_QB_CSR_SIZE 5168 +#define DDRPHY_QB_ACSM_SIZE (4 * 1024) +#define DDRPHY_QB_MSB_SIZE 0x200 +#define DDRPHY_QB_PSTATES 0 +#define DDRPHY_QB_PST_SIZE (DDRPHY_QB_PSTATES * 4 * 1024) + +/** + * This structure needs to be aligned with the one in OEI. + */ +struct ddrphy_qb_state { + u32 crc; /* Used for ensuring integrity in DRAM */ +#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */ + u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */ + u8 trained_vrefca_a0; + u8 trained_vrefca_a1; + u8 trained_vrefca_b0; + u8 trained_vrefca_b1; + u8 trained_vrefdq_a0; + u8 trained_vrefdq_a1; + u8 trained_vrefdq_b0; + u8 trained_vrefdq_b1; + u8 trained_vrefdqu_a0; + u8 trained_vrefdqu_a1; + u8 trained_vrefdqu_b0; + u8 trained_vrefdqu_b1; + u8 trained_dramdfe_a0; + u8 trained_dramdfe_a1; + u8 trained_dramdfe_b0; + u8 trained_dramdfe_b1; + u8 trained_dramdca_a0; + u8 trained_dramdca_a1; + u8 trained_dramdca_b0; + u8 trained_dramdca_b1; + u16 qb_pll_upll_prog0; + u16 qb_pll_upll_prog1; + u16 qb_pll_upll_prog2; + u16 qb_pll_upll_prog3; + u16 qb_pll_ctrl1; + u16 qb_pll_ctrl4; + u16 qb_pll_ctrl5; + u16 csr[DDRPHY_QB_CSR_SIZE]; + u16 acsm[DDRPHY_QB_ACSM_SIZE]; + u16 pst[DDRPHY_QB_PST_SIZE]; +}; + void ddr_load_train_firmware(enum fw_type type); int ddr_init(struct dram_timing_info *timing_info); int ddr_cfg_phy(struct dram_timing_info *timing_info); diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index dead7a99a66..b5e7d7d6855 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -23,6 +23,10 @@ int low_drive_freq_update(void *blob); enum imx9_soc_voltage_mode soc_target_voltage_mode(void); int get_reset_reason(bool sys, bool lm); +int scmi_get_boot_device_offset(unsigned long *img_off); +int scmi_get_boot_stage(u8 *stage); +u8 scmi_get_imgset_sel(void); + #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode)) #endif diff --git a/arch/arm/include/asm/mach-imx/ahab.h b/arch/arm/include/asm/mach-imx/ahab.h index 4884f056251..dad170cee47 100644 --- a/arch/arm/include/asm/mach-imx/ahab.h +++ b/arch/arm/include/asm/mach-imx/ahab.h @@ -8,7 +8,7 @@ #include <imx_container.h> -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length); +void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length); int ahab_auth_release(void); int ahab_verify_cntr_image(struct boot_img_t *img, int image_index); diff --git a/arch/arm/include/asm/mach-imx/qb.h b/arch/arm/include/asm/mach-imx/qb.h new file mode 100644 index 00000000000..a874c9c5e36 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/qb.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2026 NXP + */ + +#ifndef __IMX_QB_H__ +#define __IMX_QB_H__ + +#include <stdbool.h> + +bool imx_qb_check(void); +int imx_qb(const char *ifname, const char *dev, bool save); +void spl_imx_qb_save(void); + +#endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index e4014226582..66142a835ce 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -71,10 +71,38 @@ config CSF_SIZE Define the maximum size for Command Sequence File (CSF) binary this information is used to define the image boot data. +config IMX_QB + bool "Support Quickboot flow for Synopsis DDR PHY on iMX platforms" + default y + depends on IMX94 || IMX95 || IMX952 + help + Enable the logic for saving DDR training data from volatile + memory to non-volatile storage. OEI uses the saved data to + run Quickboot flow and skip re-training the DDR PHY. + +config SPL_IMX_QB + bool "Run qb save during SPL" + depends on SPL && IMX_QB + help + Automatically save DDR training data (Quickboot data) + to current boot device when needed (when OEI runs Training + flow and saves qb data to volatile memory). + +config CMD_IMX_QB + bool "Support the 'qb' command" + default y + depends on IMX_QB + help + Enable qb command to write/erase DDR quick boot training + data to/from a chosen boot device. Using 'qb save/erase' + without arguments implies using the current boot device's + first bootable partition (e.g. boot0 for eMMC). For use in + uuu scripts, the boot device must be specified explicitly. + config CMD_BMODE bool "Support the 'bmode' command" default y - depends on ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + depends on IMX95 || ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5 help This enables the 'bmode' (bootmode) command for forcing a boot from specific media. diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index bf6820de655..43febc10460 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -80,6 +80,7 @@ endif ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o +obj-$(CONFIG_CMD_IMX_QB) += cmd_qb.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o endif diff --git a/arch/arm/mach-imx/cmd_qb.c b/arch/arm/mach-imx/cmd_qb.c new file mode 100644 index 00000000000..633d83d3abd --- /dev/null +++ b/arch/arm/mach-imx/cmd_qb.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2024-2026 NXP + */ +#include <command.h> +#include <spl.h> +#include <stdlib.h> + +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/sys_proto.h> +#include <asm/mach-imx/qb.h> + +static void parse_qb_args(int argc, char * const argv[], + const char **ifname, const char **dev) +{ + /* qb save/erase -> use boot device */ + if (argc < 2) { + *ifname = "auto"; + return; + } + + *ifname = argv[1]; + + if (argc == 3) + *dev = argv[2]; +} + +static int do_qb(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[], bool save) +{ + const char *ifname, *dev; + + parse_qb_args(argc, argv, &ifname, &dev); + + if (imx_qb(ifname, dev, save)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_qb_check(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + return imx_qb_check() ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} + +static int do_qb_save(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + return do_qb(cmdtp, flag, argc, argv, true); +} + +static int do_qb_erase(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + return do_qb(cmdtp, flag, argc, argv, false); +} + +static struct cmd_tbl cmd_qb[] = { + U_BOOT_CMD_MKENT(check, 1, 1, do_qb_check, "", ""), + U_BOOT_CMD_MKENT(save, 3, 1, do_qb_save, "", ""), + U_BOOT_CMD_MKENT(erase, 3, 1, do_qb_erase, "", ""), +}; + +static int do_qbops(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cmd_tbl *cp; + + cp = find_cmd_tbl(argv[1], cmd_qb, ARRAY_SIZE(cmd_qb)); + + /* Drop the qb command */ + argc--; + argv++; + + if (!cp) { + printf("qb: %s: command not found\n", argv[0] ? argv[0] : " "); + return CMD_RET_USAGE; + } + + if (argc > cp->maxargs) { + printf("qb %s: too many arguments: %d > %d\n", cp->name, + argc - 1, cp->maxargs - 1); + return CMD_RET_USAGE; + } + + if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) { + printf("qb %s: repeat flag set but command is not repeatable\n", + cp->name); + return CMD_RET_SUCCESS; + } + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + qb, 4, 1, do_qbops, + "DDR Quick Boot sub system", + "check - check if quick boot data is stored in mem by training flow\n" + "qb save [interface] [dev] - save quick boot data in NVM => trigger quick boot flow\n" + "qb erase [interface] [dev] - erase quick boot data from NVM => trigger training flow\n" +); diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 9794391fb35..86b11bdf2ac 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -255,7 +255,7 @@ static void display_ahab_auth_ind(u32 event) printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]); } -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { int err; u32 resp; @@ -271,9 +271,10 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) printf("Authenticate container hdr failed, return %d, resp 0x%x\n", err, resp); display_ahab_auth_ind(resp); + return NULL; } - return err; + return (void *)IMG_CONTAINER_BASE; /* Return authenticated container header */ } int ahab_auth_release(void) @@ -327,7 +328,6 @@ int authenticate_os_container(ulong addr) { struct container_hdr *phdr; int i, ret = 0; - int err; u16 length; struct boot_img_t *img; unsigned long s, e; @@ -357,8 +357,8 @@ int authenticate_os_container(ulong addr) debug("container length %u\n", length); - err = ahab_auth_cntr_hdr(phdr, length); - if (err) { + phdr = ahab_auth_cntr_hdr(phdr, length); + if (!phdr) { ret = -EIO; goto exit; } @@ -367,7 +367,7 @@ int authenticate_os_container(ulong addr) /* Copy images to dest address */ for (i = 0; i < phdr->num_images; i++) { - img = (struct boot_img_t *)(addr + + img = (struct boot_img_t *)((ulong)phdr + sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 7bfcc9d7e9d..bdb43d138f2 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -240,6 +240,14 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) return offset; } +#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE) + int ret; + ret = scmi_get_boot_device_offset(&offset); + if (!ret) + return offset; + /* fall back to boot from primary set if get rom passover failed */ +#endif + sec_boot = check_secondary_cnt_set(&sec_set_off); if (sec_boot) printf("Secondary set selected\n"); @@ -366,10 +374,17 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc) part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) { - unsigned long sec_set_off = 0; bool sec_boot = false; - +#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE) + u8 stage; + int ret; + ret = scmi_get_boot_stage(&stage); + if (!ret) + sec_boot = (stage == 0x9); +#else + unsigned long sec_set_off = 0; sec_boot = check_secondary_cnt_set(&sec_set_off); +#endif if (sec_boot) part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1; } else if (part == EMMC_BOOT_PART_USER) { diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index f13baa871cc..71a3b341913 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; #define AHAB_HASH_TYPE_MASK 0x00000700 #define AHAB_HASH_TYPE_SHA256 0 -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { int err; @@ -37,10 +37,12 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); - if (err) + if (err) { printf("Authenticate container hdr failed, return %d\n", err); + return NULL; + } - return err; + return (void *)SEC_SECURE_RAM_BASE; /* Return authenticated container header */ } int ahab_auth_release(void) @@ -126,7 +128,7 @@ int authenticate_os_container(ulong addr) { struct container_hdr *phdr; int i, ret = 0; - int err; + __maybe_unused int err; u16 length; struct boot_img_t *img; unsigned long s, e; @@ -159,15 +161,15 @@ int authenticate_os_container(ulong addr) debug("container length %u\n", length); - err = ahab_auth_cntr_hdr(phdr, length); - if (err) { + phdr = ahab_auth_cntr_hdr(phdr, length); + if (!phdr) { ret = -EIO; goto exit; } /* Copy images to dest address */ for (i = 0; i < phdr->num_images; i++) { - img = (struct boot_img_t *)(addr + + img = (struct boot_img_t *)((ulong)phdr + sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8b0d48b07b3..0e885f97e63 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -79,11 +79,13 @@ config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MQ_REFORM2 bool "imx8mq_reform2" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Mini" @@ -308,6 +310,7 @@ config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MN_VAR_SOM bool "Variscite imx8mn_var_som" @@ -324,6 +327,7 @@ config TARGET_KONTRON_PITX_IMX8M bool "Support Kontron pITX-imx8m" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_TORADEX_SMARC_IMX8MP bool "Support Toradex SMARC iMX8M Plus module" @@ -426,6 +430,7 @@ config TARGET_LIBREM5 select IMX8MQ select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM endchoice diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 53cc97c6b47..80b697396ea 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright 2022 NXP +# Copyright 2022,2026 NXP obj-y += lowlevel_init.o @@ -12,4 +12,6 @@ endif ifneq ($(CONFIG_SPL_BUILD),y) obj-y += imx_bootaux.o -endif
\ No newline at end of file +endif + +obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 14a2bdf5762..4ccff67b7ab 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -478,6 +478,7 @@ u32 get_clk_src_rate(enum ccm_clk_src source) switch (source) { case ARM_PLL_CLK: ctrl = readl(&ana_regs->arm_pll.ctrl.reg); + break; case AUDIO_PLL_CLK: ctrl = readl(&ana_regs->audio_pll.ctrl.reg); break; diff --git a/arch/arm/mach-imx/imx9/qb.c b/arch/arm/mach-imx/imx9/qb.c new file mode 100644 index 00000000000..1a0a12de3d4 --- /dev/null +++ b/arch/arm/mach-imx/imx9/qb.c @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2024-2026 NXP + */ +#include <dm/device-internal.h> +#include <dm/uclass.h> +#include <errno.h> +#include <imx_container.h> +#include <linux/bitfield.h> +#include <mmc.h> +#include <spi_flash.h> +#include <spl.h> +#include <stdlib.h> +#include <u-boot/crc.h> + +#include <asm/arch/ddr.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/sys_proto.h> + +#define QB_STATE_LOAD_SIZE SZ_64K + +#define BLK_DEV 0 +#define SPI_DEV 1 + +#define IMG_FLAGS_IMG_TYPE_MASK 0xF +#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x)) + +#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */ + +static const struct { + const char *ifname; + const char *dev; +} imx_boot_devs[] = { + [BOOT_DEVICE_MMC1] = { "mmc", "0" }, + [BOOT_DEVICE_MMC2] = { "mmc", "1" }, + [BOOT_DEVICE_SPI] = { "spi", "" }, +}; + +static int imx_qb_get_board_boot_device(void) +{ + switch (get_boot_device()) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +static int imx_qb_get_boot_dev_str(const char **ifname, const char **dev) +{ + int boot_dev; + + if (IS_ENABLED(CONFIG_XPL_BUILD)) + boot_dev = spl_boot_device(); + else + boot_dev = imx_qb_get_board_boot_device(); + + if (boot_dev == BOOT_DEVICE_NONE || boot_dev == BOOT_DEVICE_BOARD) + return -EINVAL; + + *ifname = imx_boot_devs[boot_dev].ifname; + *dev = imx_boot_devs[boot_dev].dev; + + return 0; +} + +bool imx_qb_check(void) +{ + struct ddrphy_qb_state *qb_state; + u32 size, crc; + + /** + * Ensure CRC is not empty, the reason is that + * the data is invalidated after first save run + * or after it is overwritten. + */ + qb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE; + size = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc); + crc = crc32(0, (u8 *)qb_state->mac, size); + + if (!qb_state->crc || crc != qb_state->crc) + return false; + + return true; +} + +static int imx_qb_get_blk_boot_part(const char * const ifname, + const char * const dev, + struct blk_desc **bdesc) +{ + struct udevice *udev; + struct disk_partition info; + struct mmc *mmc; + int part; + int ret; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return blk_get_device_part_str(ifname, dev, bdesc, &info, 1); + + /** + * SPL does not have access to part_get_info, + * so get the partition manually. Currently only + * supporting MMC devices. + */ + ret = blk_get_device_by_str(ifname, dev, bdesc); + + if (ret < 0) + return -ENODEV; + + if ((*bdesc)->uclass_id != UCLASS_MMC) + return -EOPNOTSUPP; + + udev = dev_get_parent((*bdesc)->bdev); + mmc = mmc_get_mmc_dev(udev); + + if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) + return 0; + + part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) + return part; + + return 0; +} + +static ulong imx_qb_get_boot_device_offset(void *dev, int dev_type) +{ + struct blk_desc *bdesc; + + switch (dev_type) { + case BLK_DEV: + bdesc = dev; + + /* eMMC boot partition */ + if (bdesc->hwpart) + return CONTAINER_HDR_EMMC_OFFSET; + + return CONTAINER_HDR_MMCSD_OFFSET; + case SPI_DEV: + return CONTAINER_HDR_QSPI_OFFSET; + default: + return -EOPNOTSUPP; + } +} + +static int imx_qb_parse_container(void *addr, u64 *qb_data_off) +{ + struct container_hdr *phdr; + struct boot_img_t *img_entry; + u32 img_type, img_end; + int i; + + phdr = addr; + if (phdr->tag != 0x87 || (phdr->version != 0x0 && phdr->version != 0x2)) + return -EINVAL; + + img_entry = addr + sizeof(struct container_hdr); + for (i = 0; i < phdr->num_images; i++) { + img_type = IMG_FLAGS_IMG_TYPE(img_entry->hab_flags); + if (img_type == IMG_TYPE_DDR_TDATA_DUMMY && img_entry->size == 0) { + /* Image entry pointing to DDR Training Data */ + *qb_data_off = img_entry->offset; + return 0; + } + + img_end = img_entry->offset + img_entry->size; + if (i + 1 < phdr->num_images) { + img_entry++; + if (img_end + QB_STATE_LOAD_SIZE == img_entry->offset) { + /* hole detected */ + *qb_data_off = img_end; + return 0; + } + } + } + + return -EINVAL; +} + +static int imx_qb_get_dev_qbdata_offset(void *dev, int dev_type, ulong offset, + u64 *qbdata_offset) +{ + struct blk_desc *bdesc; + u8 *buf; + ulong count; + int ret; + + buf = malloc(CONTAINER_HDR_ALIGNMENT); + if (!buf) + return -ENOMEM; + + switch (dev_type) { + case BLK_DEV: + bdesc = dev; + + count = blk_dread(bdesc, + offset / bdesc->blksz, + CONTAINER_HDR_ALIGNMENT / bdesc->blksz, + buf); + if (count == 0) { + printf("Read container image from MMC/SD failed\n"); + ret = -EIO; + goto imx_qb_get_dev_qbdata_offset_exit; + } + break; + case SPI_DEV: + if (!CONFIG_IS_ENABLED(SPI)) { + ret = -EOPNOTSUPP; + goto imx_qb_get_dev_qbdata_offset_exit; + } + + ret = spi_flash_read_dm(dev, offset, + CONTAINER_HDR_ALIGNMENT, buf); + if (ret) { + printf("Read container header from SPI failed\n"); + ret = -EIO; + goto imx_qb_get_dev_qbdata_offset_exit; + } + break; + default: + printf("Support for device %d not enabled\n", dev_type); + ret = -EOPNOTSUPP; + goto imx_qb_get_dev_qbdata_offset_exit; + } + + ret = imx_qb_parse_container(buf, qbdata_offset); + +imx_qb_get_dev_qbdata_offset_exit: + free(buf); + + return ret; +} + +static int imx_qb_get_qbdata_offset(void *dev, int dev_type, + u64 *qbdata_offset) +{ + u64 cont_offset; + int ret, i; + + cont_offset = imx_qb_get_boot_device_offset(dev, dev_type); + + for (i = 0; i < 3; i++) { + ret = imx_qb_get_dev_qbdata_offset(dev, dev_type, cont_offset, + qbdata_offset); + if (ret == 0) { + (*qbdata_offset) += cont_offset; + break; + } + + cont_offset += CONTAINER_HDR_ALIGNMENT; + } + + return ret; +} + +static int imx_qb_blk(const char * const ifname, + const char * const dev, bool save) +{ + struct blk_desc *bdesc; + u64 offset; + u64 load_size; + int part, orig_part; + int ret; + + part = imx_qb_get_blk_boot_part(ifname, dev, &bdesc); + + if (part < 0) { + printf("Failed to find %s %s\n", ifname, dev); + return -ENODEV; + } + + orig_part = bdesc->hwpart; + + ret = blk_dselect_hwpart(bdesc, part); + if (ret && ret != -EMEDIUMTYPE) { + printf("Failed to select hwpart, ret %d\n", ret); + return ret; + } + + ret = imx_qb_get_qbdata_offset(bdesc, BLK_DEV, &offset); + if (ret) { + printf("get_qbdata_offset failed, ret = %d\n", ret); + return ret; + } + + offset /= bdesc->blksz; + load_size = QB_STATE_LOAD_SIZE / bdesc->blksz; + + if (save) { + /* QB data is stored in DDR -> can use it as buf */ + ret = blk_dwrite(bdesc, offset, load_size, + (const void *)CONFIG_QB_SAVED_STATE_BASE); + } else { + /* erase */ + ret = blk_derase(bdesc, offset, load_size); + } + + if (!ret) { + printf("Failed to write to block device\n"); + return -EIO; + } + + /* Return to original partition */ + ret = blk_dselect_hwpart(bdesc, orig_part); + if (ret && ret != -EMEDIUMTYPE) { + printf("Failed to select hwpart, ret %d\n", ret); + return ret; + } + + return 0; +} + +static int imx_qb_spi(bool save) +{ + struct udevice *flash; + u64 offset; + int ret; + + if (!CONFIG_IS_ENABLED(SPI)) { + printf("SPI not enabled\n"); + return -EOPNOTSUPP; + } + + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &flash); + if (ret) { + printf("SPI flash not found.\n"); + return -ENODEV; + } + + ret = imx_qb_get_qbdata_offset(flash, SPI_DEV, &offset); + if (ret) { + printf("get_qbdata_offset failed, ret = %d\n", ret); + return ret; + } + + ret = spi_flash_erase_dm(flash, offset, QB_STATE_LOAD_SIZE); + + if (ret) + return ret; + + if (!save) + return 0; + + /* QB data is stored in DDR -> can use it as buf */ + ret = spi_flash_write_dm(flash, offset, + QB_STATE_LOAD_SIZE, + (const void *)CONFIG_QB_SAVED_STATE_BASE); + + return ret; +} + +int imx_qb(const char *ifname, const char *dev, bool save) +{ + int ret; + + ret = 0; + + /* Try to use boot device */ + if (!strcmp(ifname, "auto")) + ret = imx_qb_get_boot_dev_str(&ifname, &dev); + + if (ret) + return ret; + + if (save && !imx_qb_check()) + return -EINVAL; + + if (!strcmp(ifname, "spi")) + ret = imx_qb_spi(save); + else + ret = imx_qb_blk(ifname, dev, save); + + if (ret) + return ret; + + if (!save) + return 0; + + /** + * invalidate qb_state mem so that at next boot + * the check function will fail and save won't happen + */ + memset((void *)CONFIG_QB_SAVED_STATE_BASE, 0, + sizeof(struct ddrphy_qb_state)); + + return 0; +} + +void spl_imx_qb_save(void) +{ + /* Save QB data on current boot device */ + if (imx_qb("auto", "", true)) + printf("QB save failed\n"); +} diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index fbee435786c..7c107c88bb4 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -311,6 +311,13 @@ static struct mm_region imx9_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + /* QB data */ + .virt = CONFIG_QB_SAVED_STATE_BASE, + .phys = CONFIG_QB_SAVED_STATE_BASE, + .size = 0x200000UL, /* 2M */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { /* empty entry to split table entry 5 if needed when TEEs are used */ 0, }, { @@ -745,6 +752,46 @@ void build_info(void) puts("\n"); } +int scmi_get_boot_device_offset(unsigned long *img_off) +{ + int ret; + rom_passover_t rom_data = {0}; + + ret = scmi_get_rom_data(&rom_data); + if (!ret) + *img_off = rom_data.img_ofs; + + return 0; +} + +int scmi_get_boot_stage(u8 *stage) +{ + int ret; + rom_passover_t rom_data = {0}; + + ret = scmi_get_rom_data(&rom_data); + if (!ret) + *stage = rom_data.boot_stage; + + return ret; +} + +u8 scmi_get_imgset_sel(void) +{ + rom_passover_t rdata = { 0 }; + int ret = scmi_get_rom_data(&rdata); + + if (!ret) + return rdata.img_set_sel; + + return 0; +} + +int boot_mode_getprisec(void) +{ + return !!scmi_get_imgset_sel(); +} + int arch_misc_init(void) { build_info(); diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 44b3e0f5310..ec0cb18e954 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -198,26 +198,15 @@ static u32 get_cpu_variant_type(u32 type) bool npu_disable = !!(val & BIT(13)); bool core1_disable = !!(val & BIT(15)); u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24); - u32 nxp_recog = (val & GENMASK(23, 16)) >> 16; + u32 speed = (val & GENMASK(11, 6)) >> 6; /* For iMX91 */ if (type == MXC_CPU_IMX91) { - switch (nxp_recog) { - case 0x9: - case 0xA: + if ((val2 & pack_9x9_fused) == pack_9x9_fused) type = MXC_CPU_IMX9111; - break; - case 0xD: - case 0xE: - type = MXC_CPU_IMX9121; - break; - case 0xF: - case 0x10: - type = MXC_CPU_IMX9101; - break; - default: - break; /* 9131 as default */ - } + + if (speed == 0xf) /* 800Mhz arm */ + type += 1; return type; } diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 8b23d48a854..2ad9499ef46 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -12,6 +12,54 @@ static struct fuse_entry_desc mx6_fuse_descs[] = { #if defined(CONFIG_MX6ULL) + {MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22}, + {MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22}, + {MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23}, + {MODULE_EPDC, "/soc/bus@2200000/epdc@228c000", 0x430, 24}, + {MODULE_ESAI, "/soc/bus@2000000/spba-bus@2000000/esai@2024000", 0x430, 25}, + {MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26}, + {MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27}, + {MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2}, + {MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3}, + {MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3}, + {MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4}, + {MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4}, + {MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5}, + {MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5}, + {MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6}, + {MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6}, + {MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7}, + {MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8}, + {MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9}, + {MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10}, + {MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11}, + {MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12}, + {MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13}, + {MODULE_DCP, "/soc/bus@2200000/dcp@2280000", 0x440, 14}, + {MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15}, + {MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24}, + {MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24}, + {MODULE_DCP_CRYPTO, "/soc/bus@2200000/dcp@2280000", 0x440, 25}, + {MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26}, + {MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26}, + {MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26}, + {MODULE_UART8, "/soc/bus@2200000/serial@2288000", 0x440, 26}, + {MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27}, + {MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27}, + {MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27}, + {MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28}, + {MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29}, + {MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29}, + {MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30}, + {MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30}, + {MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31}, + {MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22}, {MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23}, {MODULE_EPDC, "/soc/aips-bus@2200000/epdc@228c000", 0x430, 24}, @@ -90,6 +138,55 @@ static struct fuse_entry_desc mx6_fuse_descs[] = { {MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30}, {MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31}, #elif defined(CONFIG_MX6UL) + {MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22}, + {MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22}, + {MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23}, + {MODULE_SIM1, "/soc/bus@2100000/sim@218c000", 0x430, 24}, + {MODULE_SIM2, "/soc/bus@2100000/sim@21b4000", 0x430, 25}, + {MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26}, + {MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27}, + {MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2}, + {MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3}, + {MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3}, + {MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4}, + {MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4}, + {MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5}, + {MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5}, + {MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6}, + {MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6}, + {MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7}, + {MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8}, + {MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9}, + {MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10}, + {MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11}, + {MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12}, + {MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13}, + {MODULE_CAAM, "/soc/bus@2100000/crypto@2140000", 0x440, 14}, + {MODULE_CAAM, "/soc/bus@2100000/caam@2140000", 0x440, 14}, + {MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15}, + {MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24}, + {MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24}, + {MODULE_BEE, "/soc/bus@2000000/bee@2044000", 0x440, 25}, + {MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26}, + {MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26}, + {MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26}, + {MODULE_UART8, "/soc/bus@2000000/spba-bus@2000000/serial@2024000", 0x440, 26}, + {MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27}, + {MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27}, + {MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27}, + {MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28}, + {MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29}, + {MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29}, + {MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30}, + {MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30}, + {MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31}, + {MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22}, {MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23}, {MODULE_SIM1, "/soc/aips-bus@2100000/sim@218c000", 0x430, 24}, diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c index 65924483bc8..c22435c1676 100644 --- a/arch/arm/mach-imx/priblob.c +++ b/arch/arm/mach-imx/priblob.c @@ -10,6 +10,7 @@ * to decrypt an encrypted boot image. */ +#include <config.h> #include <asm/io.h> #include <command.h> #include <fsl_sec.h> diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 1adee9a461f..e45db109f4f 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -909,8 +909,10 @@ static const struct boot_mode board_boot_modes[] = { int misc_init_r(void) { +#if defined(CONFIG_VIDEO_IPUV3) gpio_request(RGB_BACKLIGHT_GP, "lvds backlight"); gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight"); +#endif gpio_request(GP_USB_OTG_PWR, "usbotg power"); gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset"); gpio_request(IMX_GPIO_NR(2, 2), "back"); diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 40047cf6783..e20350dc5d5 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -778,7 +778,7 @@ static int sata_imx_remove(struct udevice *dev) return 0; } -struct ahci_ops sata_imx_ops = { +static const struct ahci_ops sata_imx_ops = { .port_status = dwc_ahsata_port_status, .reset = dwc_ahsata_bus_reset, .scan = dwc_ahsata_scan, diff --git a/board/kontron/pitx_imx8m/MAINTAINERS b/board/kontron/pitx_imx8m/MAINTAINERS index aad84528e33..8c43526691b 100644 --- a/board/kontron/pitx_imx8m/MAINTAINERS +++ b/board/kontron/pitx_imx8m/MAINTAINERS @@ -1,7 +1,6 @@ Kontron pITX-imx8m Board M: Heiko Thiery <[email protected]> S: Maintained -F: arch/arm/dts/imx8mq-kontron-pitx-imx8m* F: board/kontron/pitx_imx8m/* F: include/configs/kontron_pitx_imx8m.h F: configs/kontron_pitx_imx8m_defconfig diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c index 27cd82e745a..cd7d79b382d 100644 --- a/board/nxp/imx8mp_evk/spl.c +++ b/board/nxp/imx8mp_evk/spl.c @@ -65,7 +65,7 @@ int power_init_board(void) * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ - if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); else pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c index 6eb0fff99f4..739a5f1f559 100644 --- a/board/nxp/imx94_evk/spl.c +++ b/board/nxp/imx94_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include <hang.h> @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,6 +45,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } static void xspi_nor_reset(void) diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c index de9256dc267..615c3b67fb6 100644 --- a/board/nxp/imx952_evk/spl.c +++ b/board/nxp/imx952_evk/spl.c @@ -8,6 +8,7 @@ #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> #include <asm/sections.h> #include <hang.h> #include <init.h> @@ -44,6 +45,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } static void xspi_nor_reset(void) diff --git a/board/nxp/imx95_evk/spl.c b/board/nxp/imx95_evk/spl.c index 761a1a4a0f6..2fd69447e1e 100644 --- a/board/nxp/imx95_evk/spl.c +++ b/board/nxp/imx95_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include <hang.h> @@ -13,6 +13,7 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } void board_init_f(ulong dummy) diff --git a/board/purism/librem5/MAINTAINERS b/board/purism/librem5/MAINTAINERS index 09e7f20e33c..818e1850302 100644 --- a/board/purism/librem5/MAINTAINERS +++ b/board/purism/librem5/MAINTAINERS @@ -2,7 +2,6 @@ PURISM LIBREM5 PHONE M: Angus Ainslie <[email protected]> S: Supported -F: arch/arm/dts/imx8mq-librem5* F: board/purism/librem5/ F: configs/librem5_defconfig F: include/configs/librem5.h diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index 79d021f81dc..57cd75b9b5e 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -88,6 +88,7 @@ static int read_auth_container(struct spl_image_info *spl_image, struct spl_load_info *info, ulong offset) { struct container_hdr *container = NULL; + struct container_hdr *authhdr; u16 length; int i, size, ret = 0; @@ -140,15 +141,19 @@ static int read_auth_container(struct spl_image_info *spl_image, } } + authhdr = container; + #ifdef CONFIG_AHAB_BOOT - ret = ahab_auth_cntr_hdr(container, length); - if (ret) + authhdr = ahab_auth_cntr_hdr(authhdr, length); + if (!authhdr) { + ret = -EINVAL; goto end_auth; + } #endif - for (i = 0; i < container->num_images; i++) { + for (i = 0; i < authhdr->num_images; i++) { struct boot_img_t *image = read_auth_image(spl_image, info, - container, i, + authhdr, i, offset); if (!image) { diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 9200557ca37..64e3ee04293 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-phanbell" CONFIG_TARGET_IMX8MQ_PHANBELL=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig index 66cfe95e876..23ee6278503 100644 --- a/configs/imx8mq_reform2_defconfig +++ b/configs/imx8mq_reform2_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-mnt-reform2" CONFIG_TARGET_IMX8MQ_REFORM2=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index 792bdd7494a..b216a0bb270 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mq-kontron-pitx-imx8m" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-kontron-pitx-imx8m" CONFIG_TARGET_KONTRON_PITX_IMX8M=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index d307e8308ff..7e450e2d356 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mq-librem5-r4" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-librem5-r4" CONFIG_TARGET_LIBREM5=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 0cbdc3778b7..2d5bfffa093 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-pico-pi" CONFIG_TARGET_PICO_IMX8MQ=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 8cd24aecf33..52c8e85fa5b 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -30,3 +30,4 @@ NXP Semiconductors mx6ullevk rproc psb + quickboot diff --git a/doc/board/nxp/quickboot.rst b/doc/board/nxp/quickboot.rst new file mode 100644 index 00000000000..0fd72b4e13b --- /dev/null +++ b/doc/board/nxp/quickboot.rst @@ -0,0 +1,59 @@ +.. SPDX-License-Identifier: GPL-2.0+ + Copyright 2026 NXP + +DDR QuickBoot flow +------------------ + +Some NXP SoCs (which use OEI - iMX943, iMX95, iMX952 etc.) support saving +DDR training data (collected by OEI during Training flow) from volatile +to non-volatile memory, which is then available to OEI at next cold reboot. +OEI uses the saved data to run Quickboot flow and avoid training the DDR again. +This significantly reduces the boot time. + +The location of the quickboot data in NVM is a space left in the bootloader by +mkimage, with the size of 64K. The qb command searches for this space to +save the data. Thus, the NVM should also be a boot device and contain +the bootloader at the time of the saving. + +U-Boot provides no authentication for quickboot data, only its integrity +is verified via the CRC32. The authentication is done in OEI. With +the exception of iMX95 A0/A1, which use CRC32 as well for verifying +the data, the rest of the SoCs use ELE to verify the MAC stored +in the ddrphy_qb_state structure. + +If the quickboot data in memory is not valid (CRC32 check fails), +U-Boot does not save it to NVM. So, if OEI runs Quickboot flow -> no +data is written to volatile memory -> invalid data -> no saving happens +(qb save fails during qb check). + +After successful saving, U-Boot clears the data in volatile memory so +that qb check fails at next reboot and the NVM isn't accessed again. + +There are 2 ways to save this data, both can be enabled: + +1. automatically, in SPL (by enabling CONFIG_SPL_IMX_QB) + +- this will save the data on the current boot device (e.g. SD) +- other configs specific to the boot device need to be enabled (CONFIG_SPL_MMC_WRITE for saving to eMMC/SD) +- use for: automating qb save / saving quickboot data if using Falcon mode (skipping U-Boot proper) + +2. using qb command in U-Boot console (by enabling CONFIG_CMD_IMX_QB) + +- supports saving on the current boot device, or on another, specified device. +- supports specifying the hwpartition for eMMC (for booting from boot0/boot1) +- if flashing via uuu, the command can be added in an uuu script (boot device needs to be specified) +- use 'qb erase' to force DDR re-training +- use for: saving quickboot data during flashing / controlling the NVM to save to / forcing re-training + +:: + + # To save/erase on current boot device + # For eMMC boot1, mmc 0:2 has to be specified explicitly + => qb save/erase + + # To save/erase on other boot device + => qb save/erase mmc 0 # eMMC boot0 + => qb save/erase mmc 0:1 # eMMC boot0 + => qb save/erase mmc 0:2 # eMMC boot1 + => qb save/erase mmc 1 # SD + => qb save/erase spi # NOR SPI diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index b953bca4f06..7b3dbf53dff 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -29,4 +29,11 @@ config SAVED_DRAM_TIMING_BASE after DRAM is trained, need to save the dram related timming info into memory for low power use. +config QB_SAVED_STATE_BASE + hex "Define the base address for saved QuickBoot state" + default 0x8fe00000 + help + Once DRAM is trained, the resulted training info is + saved into memory in order to be reachable from U-Boot. + endmenu diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index a309fd6f07c..e2b4fd334ec 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -239,7 +239,6 @@ static int bus_i2c_stop(struct udevice *bus) start_time = get_timer(0); while (1) { status = readl(®s->msr); - result = imx_lpci2c_check_clear_error(regs); /* stop detect flag */ if (status & LPI2C_MSR_SDF_MASK) { /* clear stop flag */ @@ -250,10 +249,13 @@ static int bus_i2c_stop(struct udevice *bus) if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) { debug("stop timeout\n"); + result = imx_lpci2c_check_clear_error(regs); return -ETIMEDOUT; } } + result = imx_lpci2c_check_clear_error(regs); + return result; } diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 666618681df..f2e838b84de 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1018,8 +1018,8 @@ config FSL_ENETC config FSL_ENETC_NETC_BLK_CTRL bool "NXP ENETC NETC blocks control driver" depends on FSL_ENETC - depends on IMX95 || IMX94 - default y if IMX95 || IMX94 + depends on IMX95 || IMX94 || IMX952 + default y if IMX95 || IMX94 || IMX952 help This driver configures Integrated Endpoint Register Block (IERB) and Privileged Register Block (PRB) of NETC. For i.MX platforms, it also diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 206f1a381bb..f393af40e27 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -18,6 +18,7 @@ #include <asm/io.h> #include <pci.h> #include <miiphy.h> +#include <linux/bitfield.h> #include <linux/bug.h> #include <linux/delay.h> #include <linux/build_bug.h> @@ -74,10 +75,36 @@ static int enetc_is_ls1028a(struct udevice *dev) pplat->vendor == PCI_VENDOR_ID_FREESCALE; } +static int enetc_dev_id_imx(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_IMX952)) { + int bus_devfn; + u32 reg[5]; + int error; + + error = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + bus_devfn = (reg[0] >> 8) & 0xffff; + + switch (bus_devfn) { + case 0: + return 0; + case 0x100: + return 1; + default: + return -EINVAL; + } + } + + return PCI_DEV(pci_get_devfn(dev)) >> 3; +} + static int enetc_dev_id(struct udevice *dev) { if (enetc_is_imx95(dev)) - return PCI_DEV(pci_get_devfn(dev)) >> 3; + return enetc_dev_id_imx(dev); if (enetc_is_ls1028a(dev)) return PCI_FUNC(pci_get_devfn(dev)); @@ -396,7 +423,7 @@ static int enetc_init_sgmii(struct udevice *dev) /* set up MAC for RGMII */ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) { - u32 old_val, val, dpx = 0; + u32 old_val, val = 0; old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); @@ -416,15 +443,14 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) val |= ENETC_PM_IFM_SSP_10; } - if (enetc_is_imx95(dev)) - dpx = ENETC_PM_IFM_FULL_DPX_IMX; + if (enetc_is_imx95(dev)) + val = u32_replace_bits(val, + phydev->duplex == DUPLEX_FULL ? 0 : 1, + ENETC_PM_IFM_FULL_DPX_IMX); else if (enetc_is_ls1028a(dev)) - dpx = ENETC_PM_IFM_FULL_DPX_LS; - - if (phydev->duplex == DUPLEX_FULL) - val |= dpx; - else - val &= ~dpx; + val = u32_replace_bits(val, + phydev->duplex == DUPLEX_FULL ? 1 : 0, + ENETC_PM_IFM_FULL_DPX_LS); if (val == old_val) return; diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c index 8577bb75632..0c87d80ea5c 100644 --- a/drivers/net/fsl_enetc_netc_blk_ctrl.c +++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c @@ -35,6 +35,7 @@ #define MII_PROT_RGMII 0x2 #define MII_PROT_SERIAL 0x3 #define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2)) +#define MII_PROT_GET(reg, port) (((reg) >> ((port) << 2)) & 0xf) #define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4) #define PCS_PROT_1G_SGMII BIT(0) @@ -97,6 +98,9 @@ #define IMX94_TIMER1_ID 1 #define IMX94_TIMER2_ID 2 +#define IMX952_ENETC0_BUS_DEVFN 0x0 +#define IMX952_ENETC1_BUS_DEVFN 0x100 + /* Flags for different platforms */ #define NETC_HAS_NETCMIX BIT(0) @@ -567,6 +571,69 @@ static int netc_prb_check_error(struct netc_blk_ctrl *priv) return 0; } +static int imx952_netcmix_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + ofnode child, gchild; + phy_interface_t interface; + int bus_devfn, mii_proto; + u32 val; + + /* Default setting */ + val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII); + + /* Update the link MII protocol through parsing phy-mode */ + dev_for_each_subnode(child, dev) { + if (!ofnode_is_enabled(child)) + continue; + + ofnode_for_each_subnode(gchild, child) { + if (!ofnode_is_enabled(gchild)) + continue; + + if (!ofnode_device_is_compatible(gchild, "pci1131,e101")) + continue; + + bus_devfn = netc_of_pci_get_bus_devfn(gchild); + if (bus_devfn < 0) + return -EINVAL; + + interface = ofnode_read_phy_mode(gchild); + if (interface == -1) + continue; + + mii_proto = netc_get_link_mii_protocol(interface); + if (mii_proto < 0) + return -EINVAL; + + switch (bus_devfn) { + case IMX952_ENETC0_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_0; + val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto); + break; + case IMX952_ENETC1_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_1; + val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto); + break; + default: + return -EINVAL; + } + } + } + + if (MII_PROT_GET(val, 1) == MII_PROT_SERIAL) { + /* Configure Link I/O variant */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR, + IO_VAR(1, IO_VAR_16FF_16G_SERDES)); + /* Configure Link 2 PCS protocol */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(1), + PCS_PROT_2500M_SGMII); + } + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val); + + return 0; +} + static const struct netc_devinfo imx95_devinfo = { .netcmix_init = imx95_netcmix_init, .ierb_init = imx95_ierb_init, @@ -578,9 +645,14 @@ static const struct netc_devinfo imx94_devinfo = { .xpcs_port_init = imx94_netc_xpcs_port_init, }; +static const struct netc_devinfo imx952_devinfo = { + .netcmix_init = imx952_netcmix_init, +}; + static const struct udevice_id netc_blk_ctrl_match[] = { { .compatible = "nxp,imx95-netc-blk-ctrl", .data = (ulong)&imx95_devinfo }, { .compatible = "nxp,imx94-netc-blk-ctrl", .data = (ulong)&imx94_devinfo }, + { .compatible = "nxp,imx952-netc-blk-ctrl", .data = (ulong)&imx952_devinfo }, {}, }; diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index a1e4c3d053b..9814ac498ed 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -343,7 +343,7 @@ static int nxp_c45_probe(struct phy_device *phydev) { struct nxp_c45_phy *priv; - priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL); + priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index 77c82a00b65..57af16cfbb9 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -550,6 +550,8 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV) return -EINVAL; } val = pmic_reg_read(dev->parent, desc->vsel_reg); + if (val < 0) + return val; if (desc->high_volt_mask && (val & desc->high_volt_mask)) { min_uV = desc->high_volt_desc->min_uV; uV_step = desc->high_volt_desc->uV_step; |