diff options
| author | Svyatoslav Ryhel <[email protected]> | 2024-11-18 08:32:13 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <[email protected]> | 2025-02-12 10:35:17 +0200 |
| commit | dedc0468b2eec4d4b8918742eda7203fb1871178 (patch) | |
| tree | 077236a45a4a38ef43d55f6b1ce2ca6fc4bbd787 | |
| parent | f47a02825aa967cf1f62248d50c012a3821d7ebc (diff) | |
ARM: tegra124: dts: add missing DSI nodes
Bind missing DSI and MIPI calibration devices.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
| -rw-r--r-- | arch/arm/dts/tegra124.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index ffec9cae09d..cac9b112302 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -136,6 +136,38 @@ status = "disabled"; }; + dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x54540000 0x00040000>; @@ -737,6 +769,13 @@ #thermal-sensor-cells = <1>; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0x70110000 0x100>, /* DFLL control */ |