diff options
| author | David Lechner <[email protected]> | 2026-07-06 18:52:44 -0500 |
|---|---|---|
| committer | David Lechner <[email protected]> | 2026-07-22 11:55:23 -0500 |
| commit | dfde529a780621810b0259956fc09c152e666b86 (patch) | |
| tree | 2d79ea3e74be0f277a2357ff0628aae78b30fbc4 | |
| parent | f309d23e3a171d56a4a6c2eb21588a370b8c811e (diff) | |
clk: mediatek: mt8189: fix VLP_CK wrong parents
Fix a couple of places where we used the wrong macro to set the parent
flag for vlpcfg_ao_clks.
Fixes: 04b3a834c654 ("clk: mediatek: mt8189: add some VLP clocks")
Link: https://patch.msgid.link/20260706-mtk-clk-mt8189-fix-vlp-parent-v1-1-aedc2f8cc69d@baylibre.com
Signed-off-by: David Lechner <[email protected]>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8189.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index d11947ee461..b174e259f28 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -1915,8 +1915,8 @@ static const struct mtk_gate vlpcfg_ao_clks[] = { GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SCP, CLK_VLP_CK_SCP_SEL, 28), GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_R_APXGPT_26M, CLK_PAD_CLK26M, 24), GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_DPMSRCK_TEST, CLK_PAD_CLK26M, 23), - GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22), - GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22), + GATE_VLPCFG_AO_TOP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21), GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SPMI_P_MST, CLK_VLP_CK_SPMI_P_MST_SEL, 20), GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SPMI_P_MST_32K, CLK_PAD_CLK32K, 18), GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 13), |