Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next

CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/28674

- riscv: Implement private GCC library
- mpfs: Add MPFS CPU Implementation
- andes: Stop disabling device tree relocation and some minor fixes
- sifive: Stop disabling device tree relocation
- starfive: Cleanup size types and typos

37 files changed, 427 insertions, 52 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 3133f892f94..4af0da2485f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -159,6 +159,7 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
+	select HAVE_PRIVATE_LIBGCC if 64BIT
 	select HAVE_SETJMP
 	select HAVE_INITJMP
 	select SUPPORT_ACPI
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 265b5320777..79867656b15 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -126,6 +126,7 @@ source "arch/riscv/cpu/cv1800b/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/ast2700/Kconfig"
+source "arch/riscv/cpu/mpfs/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 source "arch/riscv/cpu/jh7110/Kconfig"
 source "arch/riscv/cpu/k1/Kconfig"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d5123e4b7d9..bbadd0c9a46 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -463,7 +463,7 @@ static void riscv_parse_isa_string(const char *isa)
 		switch (*ext) {
 		case 'x':
 		case 'X':
-			log_warning("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
+			log_warning("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.\n");
 			/*
 			 * To skip an extension, we find its end.
 			 * As multi-letter extensions must be split from other multi-letter
diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig
new file mode 100644
index 00000000000..bcf1ede818b
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/Kconfig
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+config MICROCHIP_MPFS
+	bool
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SIFIVE_CLINT if RISCV_MMODE
+	imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
+	imply CMD_CPU
+	imply SPL_CPU
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
+	imply REGMAP
+	imply SYSCON
+	imply CLK_CCF
+	imply CLK_MPFS
+	imply SYS_NS16550
+	imply MACB
+	imply MII
+	imply CMD_I2C
+	imply DM_I2C
+	imply SYS_I2C_MICROCHIP
+	imply MMC
+	imply MMC_WRITE
+	imply MMC_SDHCI
+	imply MMC_SDHCI_CADENCE
+	imply MMC_SDHCI_ADMA
+	imply MMC_HS200_SUPPORT
+	imply SPI
+	imply DM_SPI
+	imply MICROCHIP_QSPI
diff --git a/arch/riscv/cpu/mpfs/Makefile b/arch/riscv/cpu/mpfs/Makefile
new file mode 100644
index 00000000000..e2f62ff7711
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/mpfs/dram.c b/arch/riscv/cpu/mpfs/dram.c
new file mode 100644
index 00000000000..4398d3e36c8
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <[email protected]>
+ */
+
+#include <asm/global_data.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_TOP_OF_CACHED (SZ_2G + SZ_1G)
+#define MPFS_HSS_RESERVATION (SZ_4M)
+
+int dram_init(void) {
+    return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void) {
+    return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size) {
+    /*
+     * Ensure that if we run from 32-bit memory that all memory used by
+     * U-Boot is cached addresses, but also account for the reservation at
+     * the top of 32 bit cached DDR used by the HSS.
+     */
+    if (gd->ram_top >= MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION)
+        return MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION - 1;
+    /*
+     * If we don't find a 32 bit region just return the top of memory.
+     * If the address is a 32-bit region, but fits beneath the HSS'
+     * reservation, ram_top is adequate also.
+     */
+    return gd->ram_top;
+}
\ No newline at end of file
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 61af6d5465e..cf2d429c7c0 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -17,8 +17,8 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
-		stdout-path = "uart0:38400n8";
+		bootargs = "console=ttyS0,115200n8 debug loglevel=7";
+		stdout-path = "uart0:115200n8";
 	};
 
 	cpus {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 8c7db29b4f2..1928221fa3c 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -17,8 +17,8 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
-		stdout-path = "uart0:38400n8";
+		bootargs = "console=ttyS0,115200n8 debug loglevel=7";
+		stdout-path = "uart0:115200n8";
 	};
 
 	cpus {
diff --git a/arch/riscv/include/asm/arch-mpfs/clk.h b/arch/riscv/include/asm/arch-mpfs/clk.h
new file mode 100644
index 00000000000..fbb1399f3c8
--- /dev/null
+++ b/arch/riscv/include/asm/arch-mpfs/clk.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_RISCV_ARCH_MPFS_CLK_H
+#define __ASM_RISCV_ARCH_MPFS_CLK_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index f1f50918eff..a527b3e9ae3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -6,6 +6,8 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <[email protected]>
 
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += clz.o ctz.o
+
 obj-$(CONFIG_$(PHASE_)LIB_BOOTM) += bootm.o
 obj-$(CONFIG_$(PHASE_)LIB_BOOTI) += image.o
 obj-$(CONFIG_CMD_GO) += boot.o
diff --git a/arch/riscv/lib/clz.c b/arch/riscv/lib/clz.c
new file mode 100644
index 00000000000..7b173d3c858
--- /dev/null
+++ b/arch/riscv/lib/clz.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count leading bits
+ *
+ * Copyright 2025, Heinrich Schuchardt <[email protected]>
+ */
+
+#include <linux/types.h>
+
+/**
+ * __clzti2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzti2(long long x)
+{
+	int ret = 64;
+
+	if (!x)
+		return 64;
+
+	if (x & 0xFFFFFFFF00000000LL) {
+		ret -= 32;
+		x >>= 32;
+	}
+	if (x & 0xFFFF0000LL) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00LL) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0LL) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xCLL) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2LL) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzsi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzsi2(int x)
+{
+	int ret = 32;
+
+	if (!x)
+		return 32;
+
+	if (x & 0xFFFF0000) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xC) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzdi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __clzti2(x);
+#else
+	return __clzsi2(x);
+#endif
+}
diff --git a/arch/riscv/lib/ctz.c b/arch/riscv/lib/ctz.c
new file mode 100644
index 00000000000..6c875e39f0e
--- /dev/null
+++ b/arch/riscv/lib/ctz.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count trailing bits
+ */
+
+#include <linux/types.h>
+
+/**
+ * __ctzti2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzti2(long long x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 64;
+
+	if (!(x & 0xFFFFFFFFLL)) {
+		ret += 32;
+		x >>= 32;
+	}
+	if (!(x & 0xFFFFLL)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFFLL)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xFLL)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3LL)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1ll))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzsi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzsi2(int x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 32;
+
+	if (!(x & 0xFFFF)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFF)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xF)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzdi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __ctzti2(x);
+#else
+	return __ctzsi2(x);
+#endif
+}
diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig
index 8dcf55a0311..d38e56c742d 100644
--- a/board/microchip/mpfs_generic/Kconfig
+++ b/board/microchip/mpfs_generic/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "microchip"
 
 config SYS_CPU
-	default "generic"
+	default "mpfs"
 
 config SYS_CONFIG_NAME
 	default "microchip_mpfs_generic"
@@ -18,15 +18,10 @@ config TEXT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select GENERIC_RISCV
+	select MICROCHIP_MPFS
 	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 	imply SMP
-	imply CLK_CCF
-	imply CLK_MPFS
-	imply REGMAP
-	imply SYSCON
-	imply SYS_NS16550
 	imply CMD_DHCP
 	imply CMD_EXT2
 	imply CMD_EXT4
@@ -39,23 +34,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply EFI_PARTITION
 	imply IP_DYN
 	imply ISO_PARTITION
-	imply MACB
-	imply MII
 	imply PHY_LIB
 	imply PHY_VITESSE
-	imply MMC
-	imply MMC_WRITE
-	imply MMC_SDHCI
-	imply MMC_SDHCI_CADENCE
-	imply MMC_SDHCI_ADMA
-	imply MMC_HS200_SUPPORT
-	imply CMD_I2C
-	imply DM_I2C
-	imply SYS_I2C_MICROCHIP
-	imply MTD
-	imply SPI
-	imply DM_SPI
-	imply MICROCHIP_COREQSPI
 	imply MTD_SPI_NAND
 	imply CMD_MTD
 	imply CMD_MTDPARTS
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 3b7b6cafef8..a4327167164 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -787,6 +787,7 @@ config SPL_FS_LOAD_PAYLOAD_NAME
 	string "File to load for U-Boot from the filesystem"
 	depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_SEMIHOSTING
 	default "tispl.bin" if SYS_K3_SPL_ATF
+	default "linux.itb" if SPL_LOAD_FIT_OPENSBI_OS_BOOT
 	default "u-boot.itb" if SPL_LOAD_FIT
 	default "linux.itb" if SPL_LOAD_FIT_OPENSBI_OS_BOOT
 	default "u-boot.img"
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index e87782005f1..973ca298a05 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -45,7 +45,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig
index f1d88f8560f..b8049aa8abc 100644
--- a/configs/ae350_rv32_falcon_defconfig
+++ b/configs/ae350_rv32_falcon_defconfig
@@ -53,7 +53,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig
index 2355bac5019..4ae973b6e7a 100644
--- a/configs/ae350_rv32_falcon_xip_defconfig
+++ b/configs/ae350_rv32_falcon_xip_defconfig
@@ -18,7 +18,8 @@ CONFIG_SPL_XIP=y
 CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x88600000
+CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_PBSIZE=1050
@@ -54,7 +55,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 6655cbd4a96..1e55bd48787 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -53,7 +53,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index 44a6b6534b8..d66e3a32323 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -54,7 +54,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 15f3b5c378b..3fc5b4a1a01 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -46,7 +46,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 78b9fc439ac..2da15974c37 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -45,7 +45,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig
index 81bebb1a1d4..fcaddef3150 100644
--- a/configs/ae350_rv64_falcon_defconfig
+++ b/configs/ae350_rv64_falcon_defconfig
@@ -53,7 +53,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig
index 8e1b8e20052..14d22b9d32a 100644
--- a/configs/ae350_rv64_falcon_xip_defconfig
+++ b/configs/ae350_rv64_falcon_xip_defconfig
@@ -18,7 +18,8 @@ CONFIG_SPL_XIP=y
 CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x88600000
+CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_PBSIZE=1050
@@ -54,7 +55,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 7950074642e..a85150dfc01 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -53,7 +53,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index d5882af1de1..34321d627be 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -54,7 +54,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index 46ce063c484..e03fe94dff9 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -46,7 +46,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
+CONFIG_BAUDRATE=115200
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index fa83ecfa10f..a754134a313 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -76,6 +76,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
 CONFIG_CMD_WGET=y
+CONFIG_WGET_HTTPS=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_BOARD=y
 CONFIG_DEVICE_TREE_INCLUDES="starfive-visionfive2-u-boot.dtsi"
@@ -154,3 +155,4 @@ CONFIG_USB_GADGET=y
 # CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_WDT=y
 CONFIG_WDT_STARFIVE=y
+CONFIG_MBEDTLS_LIB=y
diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c
index 6764b3ed5cc..ece6f5aae94 100644
--- a/drivers/ram/starfive/ddrcsr_boot.c
+++ b/drivers/ram/starfive/ddrcsr_boot.c
@@ -231,7 +231,6 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 		mask = REG8G;
 		break;
 
-	case DDR_SIZE_16G:
 	default:
 		return;
 	};
@@ -260,7 +259,6 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 		out_le32(csrreg + REGOFFSET(0x10), 0x3c);
 		break;
 
-	case DDR_SIZE_16G:
 	default:
 		break;
 	};
@@ -286,7 +284,6 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 		break;
 
 	case DDR_SIZE_2G:
-	case DDR_SIZE_16G:
 	default:
 		break;
 	};
diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c
index efe3f8a181a..f26bc9ccaad 100644
--- a/drivers/ram/starfive/ddrphy_start.c
+++ b/drivers/ram/starfive/ddrphy_start.c
@@ -267,7 +267,6 @@ void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
 		mask = REG8G;
 		break;
 
-	case DDR_SIZE_16G:
 	default:
 		return;
 	};
diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c
index b31ed3bcf61..e151179398f 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -43,13 +43,12 @@ static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *pri
 		size = DDR_SIZE_4G;
 		break;
 
-	case 0x200000000:
+	case SZ_8G:
 		size = DDR_SIZE_8G;
 		break;
 
-	case 0x400000000:
 	default:
-		pr_err("unsupport size %lx\n", priv->info.size);
+		pr_err("Unknown DDR size %lx\n", priv->info.size);
 		return -EINVAL;
 	}
 
diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h
index c29d26b510c..3ab0b0e8fa6 100644
--- a/drivers/ram/starfive/starfive_ddr.h
+++ b/drivers/ram/starfive/starfive_ddr.h
@@ -48,7 +48,6 @@ enum ddr_size_t {
 	DDR_SIZE_2G,
 	DDR_SIZE_4G,
 	DDR_SIZE_8G,
-	DDR_SIZE_16G,
 };
 
 void ddr_phy_train(u32 *phyreg);
diff --git a/include/configs/ae350.h b/include/configs/ae350.h
index 23e4801379d..43b1878b520 100644
--- a/include/configs/ae350.h
+++ b/include/configs/ae350.h
@@ -83,7 +83,6 @@
 #include <config_distro_bootcmd.h>
 
 #define CFG_EXTRA_ENV_SETTINGS	\
-				"fdt_high=0xffffffffffffffff\0" \
 				"initrd_high=0xffffffffffffffff\0" \
 				"kernel_addr_r=0x00600000\0" \
 				"kernel_comp_addr_r=0x04600000\0" \
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index cd8d0438ba6..862c2457024 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -37,7 +37,6 @@
 	"name=system,size=-,bootable,type=${type_guid_gpt_system};"
 
 #define CFG_EXTRA_ENV_SETTINGS \
-	"fdt_high=0xffffffffffffffff\0" \
 	"initrd_high=0xffffffffffffffff\0" \
 	"kernel_addr_r=0x84000000\0" \
 	"kernel_comp_addr_r=0x88000000\0" \
diff --git a/lib/Kconfig b/lib/Kconfig
index fdfe0bd5042..fe0b878a206 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -212,7 +212,7 @@ config IMAGE_SPARSE_FILLBUF_SIZE
 config USE_PRIVATE_LIBGCC
 	bool "Use private libgcc"
 	depends on HAVE_PRIVATE_LIBGCC
-	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
+	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS || RISCV)
 	help
 	  This option allows you to use the built-in libgcc implementation
 	  of U-Boot instead of the one provided by the compiler.
diff --git a/test/lib/Makefile b/test/lib/Makefile
index 35b40b584c4..7c9dc180c8d 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -10,6 +10,10 @@ obj-y += abuf.o
 obj-y += alist.o
 obj-$(CONFIG_EFI_LOADER) += efi_device_path.o efi_memory.o
 obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
+ifdef CONFIG_RISCV
+obj-$(CONFIG_USE_PRIVATE_LIBGCC) += test_clz.o
+obj-$(CONFIG_USE_PRIVATE_LIBGCC) += test_ctz.o
+endif
 obj-y += hexdump.o
 obj-$(CONFIG_SANDBOX) += kconfig.o
 obj-y += lmb.o
diff --git a/test/lib/test_clz.c b/test/lib/test_clz.c
new file mode 100644
index 00000000000..11fd527d063
--- /dev/null
+++ b/test/lib/test_clz.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2025, Heinrich Schuchardt <[email protected]>
+ */
+
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+int __clzsi2(int a);
+int __clzdi2(long a);
+int __clzti2(long long a);
+
+/**
+ * test_clz() - test library functions to count leading zero bits
+ *
+ * @uts:	unit test state
+ */
+static int test_clz(struct unit_test_state *uts)
+{
+	ut_asserteq(0, __clzti2(0xffffffffffffffffLL));
+	ut_asserteq(0, __clzti2(0x8000000000000000LL));
+	ut_asserteq(1, __clzti2(0x4000000000000000LL));
+	ut_asserteq(17, __clzti2(0x0000500000a00000LL));
+	ut_asserteq(62, __clzti2(0x0000000000000002LL));
+	ut_asserteq(63, __clzti2(0x0000000000000001LL));
+
+#if BITS_PER_LONG == 64
+	ut_asserteq(0, __clzdi2(0xffffffffffffffffLL));
+	ut_asserteq(0, __clzti2(0x8000000000000000LL));
+	ut_asserteq(1, __clzti2(0x4000000000000000LL));
+	ut_asserteq(17, __clzdi2(0x0000500000a00000LL));
+	ut_asserteq(62, __clzdi2(0x0000000000000002LL));
+	ut_asserteq(63, __clzdi2(0x0000000000000001LL));
+#else
+	ut_asserteq(0, __clzdi2(0xffffffff));
+	ut_asserteq(0, __clzdi2(0x80000000));
+	ut_asserteq(1, __clzdi2(0x40000000));
+	ut_asserteq(9, __clzdi2(0x0050a000));
+	ut_asserteq(30, __clzdi2(0x00000002));
+	ut_asserteq(31, __clzdi2(0x00000001));
+#endif
+
+	ut_asserteq(0, __clzsi2(0xffffffff));
+	ut_asserteq(0, __clzsi2(0x80000000));
+	ut_asserteq(1, __clzsi2(0x40000000));
+	ut_asserteq(9, __clzsi2(0x0050a000));
+	ut_asserteq(30, __clzsi2(0x00000002));
+	ut_asserteq(31, __clzsi2(0x00000001));
+
+	return 0;
+}
+LIB_TEST(test_clz, 0);
diff --git a/test/lib/test_ctz.c b/test/lib/test_ctz.c
new file mode 100644
index 00000000000..96c08202dc2
--- /dev/null
+++ b/test/lib/test_ctz.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2025, Heinrich Schuchardt <[email protected]>
+ */
+
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+int __ctzsi2(int a);
+int __ctzdi2(long a);
+int __ctzti2(long long a);
+
+/**
+ * test_ctz() - test library functions to count trailing zero bits
+ *
+ * @uts:	unit test state
+ */
+static int test_ctz(struct unit_test_state *uts)
+{
+	ut_asserteq(0, __ctzti2(0xffffffffffffffffLL));
+	ut_asserteq(63, __ctzti2(0x8000000000000000LL));
+	ut_asserteq(62, __ctzti2(0x4000000000000000LL));
+	ut_asserteq(21, __ctzti2(0x0000500000a00000LL));
+	ut_asserteq(1, __ctzti2(0x0000000000000002LL));
+	ut_asserteq(0, __ctzti2(0x0000000000000001LL));
+
+#if BITS_PER_LONG == 64
+	ut_asserteq(0, __ctzdi2(0xffffffffffffffffLL));
+	ut_asserteq(63, __ctzdi2(0x8000000000000000LL));
+	ut_asserteq(62, __ctzdi2(0x4000000000000000LL));
+	ut_asserteq(21, __ctzdi2(0x0000500000a00000LL));
+	ut_asserteq(1, __ctzdi2(0x0000000000000002LL));
+	ut_asserteq(0, __ctzdi2(0x0000000000000001LL));
+#else
+	ut_asserteq(0, __ctzdi2(0xffffffff));
+	ut_asserteq(31, __ctzdi2(0x80000000));
+	ut_asserteq(30, __ctzdi2(0x40000000));
+	ut_asserteq(13, __ctzdi2(0x0050a000));
+	ut_asserteq(1, __ctzdi2(0x00000002));
+	ut_asserteq(0, __ctzdi2(0x00000001));
+#endif
+
+	ut_asserteq(0, __ctzsi2(0xffffffff));
+	ut_asserteq(31, __ctzsi2(0x80000000));
+	ut_asserteq(30, __ctzsi2(0x40000000));
+	ut_asserteq(13, __ctzsi2(0x0050a000));
+	ut_asserteq(1, __ctzsi2(0x00000002));
+	ut_asserteq(0, __ctzsi2(0x00000001));
+
+	return 0;
+}
+LIB_TEST(test_ctz, 0);