diff options
| author | Michal Simek <[email protected]> | 2022-05-11 11:52:52 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2022-05-18 13:17:54 +0200 |
| commit | e4f1d2881e14145c29d5d8c05896e5bc73a15038 (patch) | |
| tree | 31ff37348739cdd59ad99dccd8505bc71dc48d14 | |
| parent | 725badc5a2e25ec4cdb163ddd78a669a7065e7fb (diff) | |
arm64: zynqmp: Add PHY description for SGMII on vck190 SC
SGMII requires phy to be configured. The support for this has been added to
Linux and U-Boot already that's why also describe the phy via DT. Clock is
coming from si5332 chip (output 1) 125MHz which is only one GT line use on
this board.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/8ad8d0c2fc9690cc90f95feddf87b0e94a685a43.1652262769.git.michal.simek@amd.com
| -rw-r--r-- | arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f229880a702..72618378230 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -42,6 +42,12 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + si5332_1: si5332_1 { /* u142 - GEM0 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; @@ -135,8 +141,17 @@ xlnx,mio-bank = <1>; }; +/* GEM SGMII */ +&psgtr { + status = "okay"; + /* gem0 */ + clocks = <&si5332_1>; + clock-names = "ref0"; +}; + &gem0 { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; |