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| author | Michal Simek <[email protected]> | 2025-12-03 08:20:32 +0100 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2025-12-19 08:25:27 +0100 |
| commit | e94fe1c16d88ed861546dc4369bf034df79bc511 (patch) | |
| tree | e56afbd6341b5eeb5424295144a8b1358de90972 | |
| parent | 38e3f9658ef8c5054999f93d3c5f97cbb485c696 (diff) | |
xilinx: mbv32: Disable floating point
MB-V 32 has optional single precision FPU (64bit has single and double
precision FPU) but there is no use and reason to enable FPU by default
that's why disable it.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/2c043ed05643fee200a79eb08bfd5c0041663bd2.1764746430.git.michal.simek@amd.com
| -rw-r--r-- | configs/xilinx_mbv32_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 88d9e5ce6b2..81c0f8e9e93 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y +# CONFIG_RISCV_ISA_F is not set # CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y |