diff options
| author | Peng Fan <[email protected]> | 2020-09-16 15:17:20 +0800 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2020-09-17 14:40:10 +0200 |
| commit | ece7844d8fbd67d078e1cb2d6807b913a2025a0c (patch) | |
| tree | c810ff1832d63f20629c985be9935294fafdfb12 | |
| parent | d81e8cf6eaebbb0a67857224781f6f7470785422 (diff) | |
imx8mq: fix SSCG_PLL_REFCLK_SEL_x
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16
Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Ye Li <[email protected]>
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 7109d334fa8..340a61e55bd 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -358,10 +358,10 @@ enum clk_src_index { #define SSCG_PLL_LOCK_SEL_MASK BIT(3) #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) #define SSCG_PLL_REFCLK_SEL_MASK 0x3 -#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0) +#define SSCG_PLL_REFCLK_SEL_OSC_27M (1) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3) #define SSCG_PLL_SSDS_MASK BIT(8) #define SSCG_PLL_SSMD_MASK (0x7 << 5) |