diff options
| author | Peng Fan <[email protected]> | 2022-04-15 12:23:37 +0800 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2022-04-21 14:38:03 +0200 |
| commit | ee5e8ee471e21633f02ea7a9ef17cdb1d30369ca (patch) | |
| tree | 602aa923de4bd80e3c0abd0c1b0471751bd8e074 | |
| parent | 0f82da2b9008360c6d1586b0a0abd780edc94c4f (diff) | |
configs: imx8qm/qxp_evk: drop unused SDHC macro
With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
CONFIG_SYS_FSL_USDHC_NUM
CONFIG_SYS_FSL_ESDHC_ADDR
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
| -rw-r--r-- | include/configs/imx8qm_mek.h | 5 | ||||
| -rw-r--r-- | include/configs/imx8qxp_mek.h | 5 |
2 files changed, 0 insertions, 10 deletions
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 0fe38e61c4b..8a269225778 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -29,10 +29,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5B010000 -#define USDHC2_BASE_ADDR 0x5B020000 - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -122,7 +118,6 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index beb35c93435..01577932884 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -27,10 +27,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5B010000 -#define USDHC2_BASE_ADDR 0x5B020000 - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -120,7 +116,6 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 |