diff options
| author | Harsimran Singh Tungal <[email protected]> | 2024-06-12 11:04:21 +0100 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-06-20 08:21:38 -0600 |
| commit | ee71d159aab66aef200c898606fcf51847d3377d (patch) | |
| tree | beec69027ad375d69dd35546c0b060147fff82e0 | |
| parent | 348385dfa09ee862ff792ce01402c9bd0af26401 (diff) | |
arm: dts: corstone1000: enable secondary cores for FVP
Add the secondary cores nodes in the dts file
Signed-off-by: Harsimran Singh Tungal <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Rui Miguel Silva <[email protected]>
| -rw-r--r-- | arch/arm/dts/corstone1000-fvp.dts | 25 | ||||
| -rw-r--r-- | arch/arm/dts/corstone1000.dtsi | 2 |
2 files changed, 26 insertions, 1 deletions
diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts index 26b0f1b3cea..3076fb9f344 100644 --- a/arch/arm/dts/corstone1000-fvp.dts +++ b/arch/arm/dts/corstone1000-fvp.dts @@ -49,3 +49,28 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; + diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi index 1e0ec075e4c..5d9d95b21cb 100644 --- a/arch/arm/dts/corstone1000.dtsi +++ b/arch/arm/dts/corstone1000.dtsi @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; |