diff options
| author | Balaji Selvanathan <[email protected]> | 2026-01-13 12:28:55 +0530 |
|---|---|---|
| committer | Casey Connolly <[email protected]> | 2026-01-14 16:25:09 +0100 |
| commit | f4886799a0afd20ab4df663247bff3c1a78a2b85 (patch) | |
| tree | d68aae0b3f561bdc1b9b7b51d90b9db674af38fc | |
| parent | 3422e915aca58faf32a80eaa3a05e7894307f81c (diff) | |
clk: qcom: sa8775p: Fix USB clock configuration and add resets
Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
[casey: indentation fix]
Signed-off-by: Casey Connolly <[email protected]>
| -rw-r--r-- | drivers/clk/qcom/clock-sa8775p.c | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index 5a6fbd417ff..4957abf6f58 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -15,8 +15,9 @@ #include <dt-bindings/clock/qcom,sa8775p-gcc.h> #include "clock-qcom.h" -#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 -#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0x1b040 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028 +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) @@ -59,8 +60,8 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) case GCC_USB30_PRIM_MASTER_CLK: WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, - 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); - clk_rcg_set_rate(priv->base, 0xf064, 0, 0); + 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); + clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; default: return 0; @@ -75,6 +76,7 @@ static const struct gate_clk sa8775p_clks[] = { GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1), GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, 1), /* QUP Wrapper 0 clocks */ GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), @@ -157,6 +159,24 @@ static const struct qcom_reset_map sa8775p_gcc_resets[] = { [GCC_TSCSS_BCR] = { 0x21000 }, [GCC_UFS_CARD_BCR] = { 0x81000 }, [GCC_UFS_PHY_BCR] = { 0x83000 }, + [GCC_USB20_PRIM_BCR] = {0x1c000}, + [GCC_USB2_PHY_PRIM_BCR] = {0x5c028}, + [GCC_USB2_PHY_SEC_BCR] = {0x5c02c}, + [GCC_USB30_PRIM_BCR] = {0x1b000}, + [GCC_USB30_SEC_BCR] = {0x2f000}, + [GCC_USB3_DP_PHY_PRIM_BCR] = {0x5c008}, + [GCC_USB3_DP_PHY_SEC_BCR] = {0x5c014}, + [GCC_USB3_PHY_PRIM_BCR] = {0x5c000}, + [GCC_USB3_PHY_SEC_BCR] = {0x5c00c}, + [GCC_USB3_PHY_TERT_BCR] = {0x5c030}, + [GCC_USB3_UNIPHY_MP0_BCR] = {0x5c018}, + [GCC_USB3_UNIPHY_MP1_BCR] = {0x5c01c}, + [GCC_USB3PHY_PHY_PRIM_BCR] = {0x5c004}, + [GCC_USB3PHY_PHY_SEC_BCR] = {0x5c010}, + [GCC_USB3UNIPHY_PHY_MP0_BCR] = {0x5c020}, + [GCC_USB3UNIPHY_PHY_MP1_BCR] = {0x5c024}, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = {0x76000}, + [GCC_VIDEO_BCR] = {0x34000} }; static const struct qcom_power_map sa8775p_gdscs[] = { |