riscv: fix the wrong swap value register

Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value

Signed-off-by: Brad Kim <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
Reviewed-by: Leo Liang <[email protected]>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bbc737ed9a2..8589509e012 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -123,7 +123,7 @@ call_board_init_f_0:
 	 * wait for initialization to complete.
 	 */
 	la	t0, hart_lottery
-	li	s2, 1
+	li	t1, 1
 	amoswap.w s2, t1, 0(t0)
 	bnez	s2, wait_for_gd_init
 #else