diff options
| author | Joonyoung Shim <[email protected]> | 2014-12-22 19:46:30 +0900 |
|---|---|---|
| committer | Minkyu Kang <[email protected]> | 2014-12-24 10:56:24 +0900 |
| commit | fb56435f504b401e3a4e66fc98098f1de447c789 (patch) | |
| tree | d189fc3409ef41889aa360350e9c730efcec7fd4 | |
| parent | 68904c83226d8bd519d7937958df578b26719ce2 (diff) | |
arm: exynos: clock: support SPLL as mmc source clock for exynos5420
MMC of exynos5420 can select SPLL as source clock, so add to support
SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board.
Signed-off-by: Joonyoung Shim <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135bebf..b31c13b14bf 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index) if (sel == 0x3) sclk = get_pll_clk(MPLL); + else if (sel == 0x4) + sclk = get_pll_clk(SPLL); else if (sel == 0x6) sclk = get_pll_clk(EPLL); else |