diff options
| author | Álvaro Fernández Rojas <[email protected]> | 2018-01-23 17:15:00 +0100 |
|---|---|---|
| committer | Jagan Teki <[email protected]> | 2018-01-24 12:03:43 +0530 |
| commit | ff159286a760b09090e46de04dd0d1ad5f70679a (patch) | |
| tree | 16cf07ca8f3cf14b3c2e4b6ff1735c9ba88f8fc3 | |
| parent | 0adfb199cead1c170a1d4cd4d3b90f4a3cd8ef52 (diff) | |
mips: bmips: add bcm63xx-spi driver support for BCM6348
This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
| -rw-r--r-- | arch/mips/dts/brcm,bcm6348.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index 711b643b5a4..540b9fea5ba 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6348"; + aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -118,6 +122,19 @@ status = "disabled"; }; + spi: spi@fffe0c00 { + compatible = "brcm,bcm6348-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6348_CLK_SPI>; + resets = <&periph_rst BCM6348_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe2300 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe2300 0x38>; |