diff options
| author | Simon Glass <[email protected]> | 2023-02-05 15:35:48 -0700 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-02-09 16:32:25 -0500 |
| commit | ffff21fb27291227f6ae680b45b88147e2cb2a87 (patch) | |
| tree | 73d6de8ffa913c9d58327dbcaca8b3ddf968c161 | |
| parent | 81e8a51cee2b265e26272f0c67518c4844baa36c (diff) | |
x86: Correct Chrromebook typo
Fix a typo in a comment.
Signed-off-by: Simon Glass <[email protected]>
| -rw-r--r-- | arch/x86/lib/fsp/fsp_dram.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 2bd408d0c56..cc889a688d8 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -60,7 +60,7 @@ int dram_init_banksize(void) * * However it seems FSP2's behavior is different. We need to add the * DRAM range in MTRR otherwise the boot process goes very slowly, - * which was observed on Chrromebook Coral with FSP2. + * which was observed on Chromebook Coral with FSP2. */ update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); |