diff options
| author | Julien Stephan <[email protected]> | 2026-07-28 14:28:23 +0200 |
|---|---|---|
| committer | David Lechner <[email protected]> | 2026-08-05 15:05:37 -0500 |
| commit | 6a77840b2f01e98bbad157fd1984a2dce2a3eecd (patch) | |
| tree | 43eb3d5bf908872b56046445e3b0b082f145bbc5 /api/api_net.c | |
| parent | cdc0564d4f4a38c924c709007dee51a5a9bd6a0d (diff) | |
clk: mediatek: mt8188: fix top0 gate polarity
Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
the clock is currently disabling them.
Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
active-high semantics.
Signed-off-by: Julien Stephan <[email protected]>
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Link: https://patch.msgid.link/20260728-mt8188-clk-fix-top0-gate-polarity-v1-1-56bc92ba6055@baylibre.com
Signed-off-by: David Lechner <[email protected]>
Diffstat (limited to 'api/api_net.c')
0 files changed, 0 insertions, 0 deletions