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authorTom Rini <[email protected]>2018-01-17 13:48:35 -0500
committerTom Rini <[email protected]>2018-01-17 13:48:35 -0500
commit086ebcd40e9bf8efc520f1b177fd8e3cc0e506fa (patch)
treee25d93fda4ce7cd672e7340f60015ec6fe2de27f /arch/arm/cpu
parent3759df0c0810636b31fe64c56868aa831514e509 (diff)
parent2eb2dbd4577898bf289e911b2286df3f2363af6e (diff)
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/Kconfig5
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c4
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 12aba9d4e9c..3a0e129d2e6 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -85,11 +85,12 @@ endmenu
config PSCI_RESET
bool "Use PSCI for reset and shutdown"
default y
- depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
+ depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
- !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && \
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 1e0030cbfba..70a60709357 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -578,7 +578,7 @@ int timer_init(void)
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
#endif
@@ -597,7 +597,7 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable