diff options
| author | Andre Przywara <[email protected]> | 2025-02-10 00:25:29 +0000 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-04-28 12:45:44 -0600 |
| commit | 1d26da5a6abaa9ef9cecce2df382d564458de6d8 (patch) | |
| tree | 2024e3214e6b769b2a7f9d7a0c791b7fde51dab4 /arch/arm/cpu | |
| parent | 5a9014a8ea3823c469f421df3d3ba667326f8a2c (diff) | |
sunxi: armv8: FEL: save and restore SP_IRQ
Thanks for Jernej's JTAG debugging effort, it turns out that the BROM
expects SP_IRQ to be saved and restored, when we want to enter back into
FEL after the SPL's AArch64 stint.
Save and restore SP_IRQ as part of the FEL state handling. The banked
MRS/MSR access to SP_IRQ, without actually being in IRQ mode, was
introduced with the ARMv7 virtualisation extensions. The Arm Cortex-A8
cores used in the A10/A13s or older F1C100s SoCs would not support that,
but this code here is purely in the ARMv8/AArch64 code path, so it's
safe to use unconditionally.
Reported-by: Jernej Skrabec <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fel_utils.S | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index f9d0c9e1d0a..044a7c16cc5 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -74,15 +74,17 @@ back_in_32: .word 0xf57ff06f // isb .word 0xe590d000 // ldr sp, [r0] .word 0xe590e004 // ldr lr, [r0, #4] + .word 0xe5901014 // ldr r1, [r0, #20] + .word 0xe121f301 // msr SP_irq, r1 .word 0xe5901010 // ldr r1, [r0, #16] .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR .word 0xe590100c // ldr r1, [r0, #12] .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR .word 0xf57ff06f // isb #ifdef CONFIG_MACH_SUN55I_A523 - .word 0xe5901014 // ldr r1, [r0, #20] - .word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR .word 0xe5901018 // ldr r1, [r0, #24] + .word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR + .word 0xe590101c // ldr r1, [r0, #28] .word 0xee0c1ffc // mcr 15, 0, r1, cr12, cr12, {7}; ICC_IGRPEN1 #endif |