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authorMichal Simek <[email protected]>2024-04-16 08:55:19 +0200
committerTom Rini <[email protected]>2024-04-22 11:01:48 -0600
commit81f3a665ab2a63a31ec7a4d760b0ce8130f62a1d (patch)
treeea17474c16b46c0710b48b1cf875bc608e9c7f9d /arch/arm/cpu
parent5a6cf7c5d54769d2500e796702f6d210907ea7e4 (diff)
common: Convert *.c/h from UTF-8 to ASCII enconfing
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Tom Rini <[email protected]> Acked-by: Marek Behún <[email protected]>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index 1541dfb3ec4..b1bb29bcaf5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -258,7 +258,7 @@ int setup_serdes_volt(u32 svdd)
/* Wait for SVDD to stabilize */
udelay(100);
- /* For each PLL that’s not disabled via RCW */
+ /* For each PLL that's not disabled via RCW */
#ifdef CONFIG_SYS_FSL_SRDS_1
cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index c0efc341afc..fbd5fd7d433 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -483,7 +483,7 @@ int setup_serdes_volt(u32 svdd)
ret = -1;
}
- /* For each PLL that’s not disabled via RCW enable the SERDES */
+ /* For each PLL that's not disabled via RCW enable the SERDES */
#ifdef CONFIG_SYS_FSL_SRDS_1
cfg_tmp = cfg_rcwsrds1 & 0x3;
do_serdes_enable(cfg_tmp, serdes1_base);