diff options
| author | Dinh Nguyen <[email protected]> | 2015-03-30 17:01:04 -0500 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2015-04-21 12:23:16 +0200 |
| commit | c218f85ea18d57beecc36a3460f08e929d81fcd6 (patch) | |
| tree | 571883d5c89a89ec5ef17b3b1c3835748d9c94c9 /arch/arm/cpu | |
| parent | 6868160ab1b55252206b983ef86770e4f778ec45 (diff) | |
arm: socfpga: add functions to bring sdram, timer, and uart out of reset
These functions will be needed for use by the SPL for enabling the
console and sdram initialization.
Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 25921e76c41..45b352bdfc0 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -113,3 +113,27 @@ void socfpga_spim_enable(void) clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } + +/* Bring UART0 out of reset. */ +void socfpga_uart0_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB); +} + +/* Bring SDRAM controller out of reset. */ +void socfpga_sdram_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB); +} + +/* Bring OSC1 timer out of reset. */ +void socfpga_osc1timer_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB); +} |
