arm: Remove aspenite board

This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last armada100 platform, remove that support
as well.

Cc: Prafulla Wadaskar <[email protected]>
Signed-off-by: Tom Rini <[email protected]>

5 files changed, 0 insertions, 416 deletions

diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 98aafe805a2..a6b29af8f4c 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -12,7 +12,6 @@ extra-y	:=
 endif
 endif
 
-obj-$(CONFIG_ARMADA100) += armada100/
 obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
deleted file mode 100644
index 77ac0e2624a..00000000000
--- a/arch/arm/cpu/arm926ejs/armada100/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <[email protected]>
-
-obj-y	= cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
deleted file mode 100644
index 96726b3144e..00000000000
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <[email protected]>
- * Contributor: Mahavir Jain <[email protected]>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-
-#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID	(1<<8)
-#define L2C_RAM_SEL	(1<<4)
-
-int arch_cpu_init(void)
-{
-	u32 val;
-	struct armd1cpu_registers *cpuregs =
-		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
-	struct armd1apb1_registers *apb1clkres =
-		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-
-	struct armd1mpmu_registers *mpmu =
-		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-
-	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
-	val = readl(&cpuregs->cpu_conf);
-	val = val | SET_MRVL_ID;
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Enable Clocks for all hardware units */
-	writel(0xFFFFFFFF, &mpmu->acgr);
-
-	/* Turn on AIB and AIB-APB Functional clock */
-	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
-
-	/* ensure L2 cache is not mapped as SRAM */
-	val = readl(&cpuregs->cpu_conf);
-	val = val & ~(L2C_RAM_SEL);
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Enable GPIO clock */
-	writel(APBC_APBCLK, &apb1clkres->gpio);
-
-#ifdef CONFIG_I2C_MV
-	/* Enable general I2C clock */
-	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
-	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
-
-	/* Enable power I2C clock */
-	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
-	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
-#endif
-
-	/*
-	 * Enable Functional and APB clock at 14.7456MHz
-	 * for configured UART console
-	 */
-#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
-	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
-#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
-	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
-#else
-	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
-#endif
-	icache_enable();
-
-	return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 id;
-	struct armd1cpu_registers *cpuregs =
-		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
-	id = readl(&cpuregs->chip_id);
-	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
deleted file mode 100644
index c97b5b1940a..00000000000
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <[email protected]>,
- * Contributor: Mahavir Jain <[email protected]>
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * ARMADA100 DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet Appendix A.17
- */
-struct armd1ddr_map_registers {
-	u32	cs;	/* Memory Address Map Register -CS */
-	u32	pad[3];
-};
-
-struct armd1ddr_registers {
-	u8	pad[0x100 - 0x000];
-	struct armd1ddr_map_registers mmap[2];
-};
-
-/*
- * armd1_sdram_base - reads SDRAM Base Address Register
- */
-u32 armd1_sdram_base(int chip_sel)
-{
-	struct armd1ddr_registers *ddr_regs =
-		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
-	return result;
-}
-
-/*
- * armd1_sdram_size - reads SDRAM size
- */
-u32 armd1_sdram_size(int chip_sel)
-{
-	struct armd1ddr_registers *ddr_regs =
-		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs);
-	result = (result >> 16) & 0xF;
-	if (result < 0x7) {
-		printf("Unknown DRAM Size\n");
-		return -1;
-	} else {
-		return ((0x8 << (result - 0x7)) * 1024 * 1024);
-	}
-}
-
-int dram_init(void)
-{
-	int i;
-
-	gd->ram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
-		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
-		/*
-		 * It is assumed that all memory banks are consecutive
-		 * and without gaps.
-		 * If the gap is found, ram_size will be reported for
-		 * consecutive memory only
-		 */
-		if (gd->bd->bi_dram[i].start != gd->ram_size)
-			break;
-
-		gd->ram_size += gd->bd->bi_dram[i].size;
-
-	}
-
-	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-		/* If above loop terminated prematurely, we need to set
-		 * remaining banks' start address & size as 0. Otherwise other
-		 * u-boot functions and Linux kernel gets wrong values which
-		 * could result in crash */
-		gd->bd->bi_dram[i].start = 0;
-		gd->bd->bi_dram[i].size = 0;
-	}
-	return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-int dram_init_banksize(void)
-{
-	dram_init();
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
deleted file mode 100644
index 4b96d4aa918..00000000000
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ /dev/null
@@ -1,198 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <[email protected]>
- * Contributor: Mahavir Jain <[email protected]>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <time.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-/*
- * Timer registers
- * Refer Section A.6 in Datasheet
- */
-struct armd1tmr_registers {
-	u32 clk_ctrl;	/* Timer clk control reg */
-	u32 match[9];	/* Timer match registers */
-	u32 count[3];	/* Timer count registers */
-	u32 status[3];
-	u32 ie[3];
-	u32 preload[3];	/* Timer preload value */
-	u32 preload_ctrl[3];
-	u32 wdt_match_en;
-	u32 wdt_match_r;
-	u32 wdt_val;
-	u32 wdt_sts;
-	u32 icr[3];
-	u32 wdt_icr;
-	u32 cer;	/* Timer count enable reg */
-	u32 cmr;
-	u32 ilr[3];
-	u32 wcr;
-	u32 wfar;
-	u32 wsar;
-	u32 cvwr;
-};
-
-#define TIMER			0	/* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL		0xffffffff
-#define	COUNT_RD_REQ		0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/* For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-	volatile int loop=100;
-
-	writel(COUNT_RD_REQ, &armd1timers->cvwr);
-	while (loop--);
-	return(readl(&armd1timers->cvwr));
-}
-
-static ulong get_timer_masked(void)
-{
-	ulong now = read_timer();
-
-	if (now >= gd->arch.tbl) {
-		/* normal mode */
-		gd->arch.tbu += now - gd->arch.tbl;
-	} else {
-		/* we have an overflow ... */
-		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
-	}
-	gd->arch.tbl = now;
-
-	return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
-	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
-		base);
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong delayticks;
-	ulong endtime;
-
-	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
-	endtime = get_timer_masked() + delayticks;
-
-	while (get_timer_masked() < endtime);
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
-	struct armd1apb1_registers *apb1clkres =
-		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-
-	/* Enable Timer clock at 3.25 MHZ */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
-	/* load value into timer */
-	writel(0x0, &armd1timers->clk_ctrl);
-	/* Use Timer 0 Match Resiger 0 */
-	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
-	/* Preload value is 0 */
-	writel(0x0, &armd1timers->preload[TIMER]);
-	/* Enable match comparator 0 for Timer 0 */
-	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
-
-	/* Enable timer 0 */
-	writel(0x1, &armd1timers->cer);
-	/* init the gd->arch.tbu and gd->arch.tbl value */
-	gd->arch.tbl = read_timer();
-	gd->arch.tbu = 0;
-
-	return 0;
-}
-
-#define MPMU_APRR_WDTR	(1<<4)
-#define TMR_WFAR	0xbaba	/* WDT Register First key */
-#define TMP_WSAR	0xeb10	/* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu(void)
-{
-	struct armd1mpmu_registers *mpmu =
-		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-	u32 val;
-
-	/* negate hardware reset to the WDT after system reset */
-	val = readl(&mpmu->aprr);
-	val = val | MPMU_APRR_WDTR;
-	writel(val, &mpmu->aprr);
-
-	/* reset/enable WDT clock */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
-	readl(&mpmu->wdtpcr);
-	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-	readl(&mpmu->wdtpcr);
-
-	/* clear previous WDT status */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0, &armd1timers->wdt_sts);
-
-	/* set match counter */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0xf, &armd1timers->wdt_match_r);
-
-	/* enable WDT reset */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0x3, &armd1timers->wdt_match_en);
-
-	while(1);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return (ulong)CONFIG_SYS_HZ;
-}