diff options
| author | Lokesh Vutla <[email protected]> | 2013-08-23 17:34:17 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2013-09-20 16:57:40 -0400 |
| commit | e22cc0cf137149bea3a06bb29ffe06e82d8edb84 (patch) | |
| tree | 40da8d76dbf33228a3cfff8e3e2fc0899c0be7c1 /arch/arm/cpu | |
| parent | d3d33daf1112d3b1c6c330422740a4e210259f88 (diff) | |
ARM: OMAP5: Avoid writing into LDO SRAM bits
Writing magic bits into LDO SRAM was suggested only for OMAP5432
ES1.0. Now these are no longer applicable. Moreover these bits should
not be overwritten as they are loaded from EFUSE. So avoid
writing into these registers.
Boot tested on OMAP5432 ES2.0
Signed-off-by: Lokesh Vutla <[email protected]>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/clocks-common.c | 7 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 12 |
2 files changed, 0 insertions, 19 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 75805940748..ab0c5680f54 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores) val = optimize_vcore_voltage(&vcores->iva); do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); - - if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { - /* Configure LDO SRAM "magic" bits */ - writel(2, (*prcm)->prm_sldo_core_setup); - writel(2, (*prcm)->prm_sldo_mpu_setup); - writel(2, (*prcm)->prm_sldo_mm_setup); - } } static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 579818d5593..5a3d52c11a2 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = { .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, - .prm_sldo_core_setup = 0x4ae07bc4, - .prm_sldo_core_ctrl = 0x4ae07bc8, - .prm_sldo_mpu_setup = 0x4ae07bcc, - .prm_sldo_mpu_ctrl = 0x4ae07bd0, - .prm_sldo_mm_setup = 0x4ae07bd4, - .prm_sldo_mm_ctrl = 0x4ae07bd8, /* SCRM stuff, used by some boards */ .scrm_auxclk0 = 0x4ae0a310, @@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = { .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, - .prm_sldo_core_setup = 0x4ae07cc4, - .prm_sldo_core_ctrl = 0x4ae07cc8, - .prm_sldo_mpu_setup = 0x4ae07ccc, - .prm_sldo_mpu_ctrl = 0x4ae07cd0, - .prm_sldo_mm_setup = 0x4ae07cd4, - .prm_sldo_mm_ctrl = 0x4ae07cd8, .prm_abbldo_mpu_setup = 0x4ae07cdc, .prm_abbldo_mpu_ctrl = 0x4ae07ce0, |