sunxi: Add arm64 FEL support

So far we did not support the BootROM based FEL USB debug mode on the
64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the
SPL runs in AArch64.
Returning back to AArch32 was not working as expected, since the RMR
reset into 32-bit mode always starts execution in the BootROM, but not
in the FEL routine.

After some debug and research and with help via IRC, the CPU hotplug
mechanism emerged as a solution: If a certain R_CPUCFG register contains
some magic, the BootROM will immediately branch to an address stored in
some other register. This works well for our purposes.

Enable the FEL feature by providing early AArch32 code to first save the
FEL state, *before* initially entering AArch64.
If we eventually determine that we should return to FEL, we reset back
into AArch32, and use the CPU hotplug mechanism to run some small
AArch32 code snippet that restores the initially saved FEL state.

That allows the normal AArch64 SPL build to be loaded via the sunxi-fel
tool, with it returning into FEL mode, so that other payloads can be
transferred via FEL as well.

Tested on A64, H5 and H6.

Signed-off-by: Andre Przywara <[email protected]>
Tested-by: Icenowy Zheng <[email protected]>
Acked-by: Jagan Teki <[email protected]>
Tested-by: Priit Laes <[email protected]> (on Olimex A64-Olinuxino)

1 files changed, 14 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 54c144afd8c..46d0f0666c2 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -15,6 +15,19 @@
 	tst     x0, x0                  // this is "b #0x84" in ARM
 	b       reset
 	.space  0x7c
+
+	.word	0xe28f0058	// add     r0, pc, #88
+	.word	0xe59f1054	// ldr     r1, [pc, #84]
+	.word	0xe0800001	// add     r0, r0, r1
+	.word	0xe580d000	// str     sp, [r0]
+	.word	0xe580e004	// str     lr, [r0, #4]
+	.word	0xe10fe000	// mrs     lr, CPSR
+	.word	0xe580e008	// str     lr, [r0, #8]
+	.word	0xee11ef10	// mrc     15, 0, lr, cr1, cr0, {0}
+	.word	0xe580e00c	// str     lr, [r0, #12]
+	.word	0xee1cef10	// mrc     15, 0, lr, cr12, cr0, {0}
+	.word	0xe580e010	// str     lr, [r0, #16]
+
 	.word	0xe59f1024	// ldr     r1, [pc, #36] ; 0x170000a0
 	.word	0xe59f0024	// ldr     r0, [pc, #36] ; CONFIG_*_TEXT_BASE
 	.word	0xe5810000	// str     r0, [r1]
@@ -36,6 +49,7 @@
 #else
 	.word   CONFIG_SYS_TEXT_BASE
 #endif
+	.word	fel_stash - .
 #else
 /* normal execution */
 	b	reset