diff options
| author | Tom Rini <[email protected]> | 2019-02-20 12:26:05 -0500 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2019-02-20 12:26:05 -0500 |
| commit | 176b32cd4fec52307dd8234ec1c86d2f340e7a36 (patch) | |
| tree | a0cb5ffc2543573d1e5af1ddb7500d97e15b3a00 /arch/arm/include | |
| parent | 97f9830849c64d60d0cf2fd69e87dfe4557d02a4 (diff) | |
| parent | b0d4a854751b1bee75fc04fac58561212f6b9c64 (diff) | |
Merge git://git.denx.de/u-boot-fsl-qoriq
- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 |
3 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index d4f80a24cd7..903d5096c71 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -26,7 +26,6 @@ #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) -#define CONFIG_FSL_TZASC_400 #endif #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -121,8 +120,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_GICV3 -#define CONFIG_FSL_TZPC_BP147 -#define CONFIG_FSL_TZASC_400 #define CONFIG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index eaa9ed251ee..d62754e0451 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -42,7 +42,11 @@ #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#ifndef CONFIG_ARCH_LX2160A #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#else +#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 +#endif #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 #ifdef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 0535224646b..9fab88ab2ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -350,6 +350,14 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 #define FSL_CHASSIS3_SRDS3_REGSR 29 +#define FSL_CHASSIS3_RCWSR12_REGSR 12 +#define FSL_CHASSIS3_RCWSR13_REGSR 13 +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000 +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24 +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038 +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3 +#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00 +#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 |