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| author | Tom Rini <[email protected]> | 2024-06-03 18:42:11 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-06-04 08:09:09 -0600 |
| commit | 227be29df37545f74243a98c12a4a33c4160e3cd (patch) | |
| tree | 8a758001963b7b45f869385ef9d00e30faf04bd3 /arch/arm/include | |
| parent | 15d0dcc0ec1f424199dff2a3cbe037bc3a7d8749 (diff) | |
| parent | c0ea27bccfb7d2d37fd36806ac2a2f7389099420 (diff) | |
Merge tag 'v2024.07-rc4' into next
Prepare v2024.070-rc4
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index a4507e5fdd7..a0e54d39654 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -29,6 +29,7 @@ enum rk3588_pll_id { V0PLL, AUPLL, PPLL, + SPLL, PLL_COUNT, }; @@ -150,6 +151,9 @@ struct pll_rate_table { #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) +#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 0x4 + 0x220) +#define RK3588_SBUSCRU_MODE_CON0 0x280 + enum { /* CRU_CLK_SEL8_CON */ ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14, |