Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi

The bulk of it is Samuel's DM_I2C rework, which removes the nasty I2C
deprecation warnings for most 32-bit boards. It also includes some
smaller refactorings that pave the way for more changes, mostly driven
by needing to support the Allwinner RISC-V SoC later on.

Board wise we gain support for the FriendlyARM NanoPi R1S H5 router
board and official Pinetab support.

Build-tested for all 160 sunxi boards, and boot tested on a A64, A20,
H3, H6, and H616 board. USB, SD card, eMMC, and Ethernet all work there
(where applicable).

2 files changed, 2 insertions, 118 deletions

diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h
deleted file mode 100644
index cac5c5faf05..00000000000
--- a/arch/arm/include/asm/arch-sunxi/ccu.h
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Amarula Solutions.
- * Author: Jagan Teki <[email protected]>
- */
-
-#ifndef _ASM_ARCH_CCU_H
-#define _ASM_ARCH_CCU_H
-
-#ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-#endif
-
-/**
- * enum ccu_flags - ccu clock/reset flags
- *
- * @CCU_CLK_F_IS_VALID:		is given clock gate is valid?
- * @CCU_RST_F_IS_VALID:		is given reset control is valid?
- */
-enum ccu_flags {
-	CCU_CLK_F_IS_VALID		= BIT(0),
-	CCU_RST_F_IS_VALID		= BIT(1),
-};
-
-/**
- * struct ccu_clk_gate - ccu clock gate
- * @off:	gate offset
- * @bit:	gate bit
- * @flags:	ccu clock gate flags
- */
-struct ccu_clk_gate {
-	u16 off;
-	u32 bit;
-	enum ccu_flags flags;
-};
-
-#define GATE(_off, _bit) {			\
-	.off = _off,				\
-	.bit = _bit,				\
-	.flags = CCU_CLK_F_IS_VALID,		\
-}
-
-/**
- * struct ccu_reset - ccu reset
- * @off:	reset offset
- * @bit:	reset bit
- * @flags:	ccu reset control flags
- */
-struct ccu_reset {
-	u16 off;
-	u32 bit;
-	enum ccu_flags flags;
-};
-
-#define RESET(_off, _bit) {			\
-	.off = _off,				\
-	.bit = _bit,				\
-	.flags = CCU_RST_F_IS_VALID,		\
-}
-
-/**
- * struct ccu_desc - clock control unit descriptor
- *
- * @gates:	clock gates
- * @resets:	reset unit
- */
-struct ccu_desc {
-	const struct ccu_clk_gate *gates;
-	const struct ccu_reset *resets;
-};
-
-/**
- * struct ccu_priv - sunxi clock control unit
- *
- * @base:	base address
- * @desc:	ccu descriptor
- */
-struct ccu_priv {
-	void *base;
-	const struct ccu_desc *desc;
-};
-
-/**
- * sunxi_clk_probe - common sunxi clock probe
- * @dev:	clock device
- */
-int sunxi_clk_probe(struct udevice *dev);
-
-extern struct clk_ops sunxi_clk_ops;
-
-/**
- * sunxi_reset_bind() - reset binding
- *
- * @dev:       reset device
- * @count:     reset count
- * @return 0 success, or error value
- */
-int sunxi_reset_bind(struct udevice *dev, ulong count);
-
-#endif /* _ASM_ARCH_CCU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 2969a530ae1..f3ab1aea0ef 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -93,20 +93,10 @@ struct sunxi_gpio_reg {
 #define GPIO_PULL_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 
 /* GPIO bank sizes */
-#define SUNXI_GPIO_A_NR		32
-#define SUNXI_GPIO_B_NR		32
-#define SUNXI_GPIO_C_NR		32
-#define SUNXI_GPIO_D_NR		32
-#define SUNXI_GPIO_E_NR		32
-#define SUNXI_GPIO_F_NR		32
-#define SUNXI_GPIO_G_NR		32
-#define SUNXI_GPIO_H_NR		32
-#define SUNXI_GPIO_I_NR		32
-#define SUNXI_GPIO_L_NR		32
-#define SUNXI_GPIO_M_NR		32
+#define SUNXI_GPIOS_PER_BANK	32
 
 #define SUNXI_GPIO_NEXT(__gpio) \
-	((__gpio##_START) + (__gpio##_NR) + 0)
+	((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
 
 enum sunxi_gpio_number {
 	SUNXI_GPIO_A_START = 0,
@@ -148,8 +138,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPA_EMAC		2
 #define SUN6I_GPA_GMAC		2
 #define SUN7I_GPA_GMAC		5
-#define SUN6I_GPA_SDC2		5
-#define SUN6I_GPA_SDC3		4
 #define SUN8I_H3_GPA_UART0	2
 
 #define SUN4I_GPB_PWM		2
@@ -173,12 +161,10 @@ enum sunxi_gpio_number {
 #define SUN6I_GPC_SDC3		4
 #define SUN50I_GPC_SPI0		4
 
-#define SUN8I_GPD_SDC1		3
 #define SUNXI_GPD_LCD0		2
 #define SUNXI_GPD_LVDS0		3
 #define SUNXI_GPD_PWM		2
 
-#define SUN5I_GPE_SDC2		3
 #define SUN8I_GPE_TWI2		3
 #define SUN50I_GPE_TWI2		3
 
@@ -242,9 +228,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
-int sunxi_name_to_gpio_bank(const char *name);
 int sunxi_name_to_gpio(const char *name);
-#define name_to_gpio(name) sunxi_name_to_gpio(name)
 
 #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
 int axp_gpio_init(void);