diff options
| author | Andre Przywara <[email protected]> | 2022-12-02 20:30:40 +0000 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2023-10-22 23:41:51 +0100 |
| commit | 39ba474698bb4bc3dc48fd0c024f7cf06b08077a (patch) | |
| tree | 9388def037d809f9fd4cc60eb8e467a1fb0b8421 /arch/arm/include | |
| parent | b9a91b98e8d81d2f7fdbc0d59c544a7bbb5e3679 (diff) | |
sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup
The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.
Signed-off-by: Andre Przywara <[email protected]>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 37df4410eaa..9895c2c220e 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -228,6 +228,7 @@ struct sunxi_ccm_reg { /* pll1 bit field */ #define CCM_PLL1_CTRL_EN BIT(31) +#define CCM_PLL1_LDO_EN BIT(30) #define CCM_PLL1_LOCK_EN BIT(29) #define CCM_PLL1_LOCK BIT(28) #define CCM_PLL1_OUT_EN BIT(27) |