diff options
| author | Andre Przywara <[email protected]> | 2025-01-05 21:51:59 +0000 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-04-28 12:45:44 -0600 |
| commit | 5a9014a8ea3823c469f421df3d3ba667326f8a2c (patch) | |
| tree | 72048afc7e8aca18552af2c5d1bf4a7f0a5b4982 /arch/arm/include | |
| parent | 8fb6c9343dbbd980c0945560f69b5a88f2404de7 (diff) | |
sunxi: armv8: FEL: save and restore GICv3 registers
To be able to return to the BootROM FEL USB debug code, we must restore
the core's state as accurately as possible after the SPL has been run.
Since the BootROM runs in AArch32, but the SPL uses AArch64, this requires
a core reset, which clears the core's state.
So far we were saving and restoring the required registers like SCTLR
and VBAR, but could ignore the interrupt controller's state (GICC), since
that lives in MMIO registers, unaffected by a core reset.
Newer Allwinner SoCs now feature a GICv3 interrupt controller, which keeps
some GIC state in architected system registers, and those are cleared
when we switch back to AArch32.
To enable FEL operation on the Allwinner A523 SoC,
Add AArch32 assembly code to save and restore the ICC_PMR and ICC_IGRPEN1
system registers. The other GICv3 sysregs are either not relevant for the
BROM operation, or haven't been changed from their reset defaults by the
BROM anyway.
This enables FEL operation on the Allwinner A523 family of SoCs.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/boot0.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 24c81391d58..9baedc2e9af 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -30,7 +30,15 @@ .word 0xe580e00c // str lr, [r0, #12] .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} .word 0xe580e010 // str lr, [r0, #16] - +#ifdef CONFIG_MACH_SUN55I_A523 + .word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5} + .word 0xe31e0001 // tst lr, #1 + .word 0x0a000003 // beq cc <start32+0x48> + .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0} + .word 0xe580e014 // str lr, [r0, #20] + .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7} + .word 0xe580e018 // str lr, [r0, #24] +#endif .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG |