diff options
| author | Rajeshwari Shinde <[email protected]> | 2012-07-03 20:02:57 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <[email protected]> | 2012-09-01 14:58:23 +0200 |
| commit | 6071bcaec1cbbdd2679f9abdd36dfe16114bc315 (patch) | |
| tree | 142468c8d25f58f06e357b947298461c28a04dfa /arch/arm/include | |
| parent | 87f2e079dbbe517003bd2c3910ae2512ab27a6f5 (diff) | |
EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Joonyoung Shim <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/clock.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 90271f1a489..bf41c1959f1 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -596,4 +596,7 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif |