diff options
| author | Tom Rini <[email protected]> | 2021-10-20 14:24:09 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2021-10-20 14:24:09 -0400 |
| commit | 79b8849d4c1e73df2a79a1d5a5f6166d0dd67a12 (patch) | |
| tree | b630c9a63287d8586b85f2bdd00af56353c66b25 /arch/arm/include | |
| parent | 11c41192ec08ba6ded60b0d6e8257cfbd6ad1914 (diff) | |
| parent | f0045799c6957e374cc12a6146ac60881cd827d6 (diff) | |
Merge tag 'u-boot-imx-20211020' of https://source.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20211020
-------------------
First PR from u-boot-imx for 2022.01
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535
- new board: kontron-sl-mx8mm
- imx8m:
- fix secure boot
- imx ESDHC: fixes
- i.MX53: Support thum2, bmode and fixes for Menlo board
usbarmory switch to Ethernet driver model
- imx6 :
- DDR calibration for Toradex boards
- imx7:
- Fixes
- Updated gateworks boards (ventana / venice)
# gpg verification failed.
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/mach-imx/iomux-v3.h | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 1de70933550..9330a32fe98 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -87,15 +87,6 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) #ifdef CONFIG_IMX8M -#define PAD_CTL_DSE0 (0x0 << 0) -#define PAD_CTL_DSE1 (0x1 << 0) -#define PAD_CTL_DSE2 (0x2 << 0) -#define PAD_CTL_DSE3 (0x3 << 0) -#define PAD_CTL_DSE4 (0x4 << 0) -#define PAD_CTL_DSE5 (0x5 << 0) -#define PAD_CTL_DSE6 (0x6 << 0) -#define PAD_CTL_DSE7 (0x7 << 0) - #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) @@ -105,8 +96,20 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define PAD_CTL_DSE1 (0x0 << 1) +#define PAD_CTL_DSE2 (0x2 << 1) +#define PAD_CTL_DSE4 (0x1 << 1) +#define PAD_CTL_DSE6 (0x3 << 1) #define PAD_CTL_PE (0x1 << 8) #else +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) #define PAD_CTL_LVTTL (0x1 << 8) #endif |