diff options
| author | Jagan Teki <[email protected]> | 2017-09-27 23:03:10 +0530 |
|---|---|---|
| committer | Philipp Tomsich <[email protected]> | 2017-10-01 00:33:33 +0200 |
| commit | d9a7dcf5b8da5460a08305cdc9452f4e62dd34e5 (patch) | |
| tree | ed337c8ff2e94ee00af22d7d2129b575a39a0a96 /arch/arm/include | |
| parent | f3f6591ca39325f34ef3ec3600be2e493b3a0327 (diff) | |
armv7: Move L2CTLR read/write to common
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.
Cc: Tom Warren <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <[email protected]>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/armv7.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a20702e612b..efc515eb334 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -61,6 +61,27 @@ #include <asm/io.h> #include <asm/barriers.h> +/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); + isb(); +} + /* * Workaround for ARM errata # 798870 * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been |